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Preliminary Technical Data
FEATURES
Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs AD5522
PRODUCT OVERVIEW
The AD5522 is a high performance, highly integrated parametric measurement unit consisting of four independent channels. Each PPMU channel includes five, 16-bit, voltage out DACs setting the programmable inputs levels for the force voltage input, clamp and comparator inputs (high and low). Five programmable force and measure current ranges are available ranging from 5A to 64mA. Four of these ranges use on chip sense resistors, while a high current range up to 64mA is available per channel using off chip sense resistors. Currents in excess of 64mA require an external amplifier. Low capacitance DUT connections (FOH, EXT FOH) ensure the device is suited to relay less test systems. The PMU functions are controlled via a simple three wire serial interface compatible with SPI/QSPI/Microwire and DSP interface standards. Interface clocks of 50MHz allow fast updating of modes. LVDS (Low Voltage Differential Signaling) interface protocol at 100MHz is also supported. Comparator outputs are provided per channel for device go no-go testing and characterization. Control registers provide easy way of changing force or measure conditions, DAC levels and selected current ranges. SDO (serial data out) allows the user to readback information for diagnostic purposes.
Quad Parametric Measurement Unit FV, FI, FN, MV, MI Functions 4 Programmable Current Ranges (Internal RSENSE) 5uA, 20uA, 200uA and 2mA 1 Programmable Current Range up to 64mA (external RSENSE) 22.5 V FV Range with Asymmetrical Operation Integrated 16-Bit DACs Provide Programmable Levels Offset and Gain Correction on Chip Low Capacitance Outputs Suited to Relay Less Systems On-chip Comparators Per Channel FI Voltage Clamps & FV Current Clamps Guard Drive Amplifier System PMU connections Programmable Temperature Shutdown Feature SPI/Microwire/DSP & LVDS Compatible Interfaces Compact 80 lead TQFP Package with Exposed Pad (Top Or Bottom)
APPLICATIONS
Automatic Test Equipment (ATE) per pin Parametric Measurement Unit Continuity & Leakage Testing Device Power Supply Instrumentation SMU (Source Measure Unit) Precision Measurement
AGND AVSS(0-4) AVDD(0-4) DVCC DGND
CCOMP (0-3)
SYS_FORCE
SYS_SENSE
VREF
16
REFGND
16 16
X1 REG M REG C REG
16
X2 REG *2 *2
16-Bit CLH DAC
x4
FIN SW 1 AGNDx
EN
EXTFOH(0-3)
CLH SW 3
CFF(0-3)
OFFSET DAC *6
16 16 16
INTERNAL RANGE SELECT (5uA, 20uA, 200uA, 2mA)
FORCE AMPLIFER
60
1k
X1 REG M REG C REG *6
16
16-Bit FIN DAC
X2 REG
+ -
FOH(0-3) RSENSE
SW 4 SW 6 SW 7 SW 5
SW 2
16 16 16 16
X1 REG M REG C REG
X2 REG *2 *2
16-Bit CLL DAC
SW 10
OFFSET DAC BIAS TO CENTER IRANGE
CLL
EXTMEASIH(0-3) + SW 8
10k EXTMEASIL(0-3)
SW 9
+
x5 or x10
MEASOUT (0-3)
SW 12
MEASOUT MUX & GAIN x1/x0.2
TEMP SENSOR SW 11 MEASURE CURRENT IN AMP
+ -
EXTERNAL RSENSE (CURRENTS UP TO 64mA)
AGND (0-3)
16 16 16
*6 X1 REG M REG C REG *6 X1 REG M REG C REG
*6
16
MEASVH (0-3) + GUARD (0-3)
GUARD AMP SW 14 SW 16
X2 REG
16-Bit CPH DAC
AGNDx
x1
+ MEASURE VOLTAGE IN AMP
SW 13
DUT
16 16 16
CPH
*6
16
CPL 16-Bit CPL DAC
+ -
DUTGND
GUARDIN (0-3)/ DUTGND (0-3) DUTGND
X2 REG
COMPARATOR
+
-+
SW 15
10k
AGNDx
16
16-Bit OFFSET DAC
16
TO ALL DAC OUTPUT AMPLIFIERS
SERIAL INTERFACE
TO MEASOUT MUX
TEMP SENSOR CLAMP & GUARD ALARM
TMPALM
POWER ON RESET
CGALM
RESET
SDO
SCLK SDI SYNC BUSY
LOAD
LVDS/ CPOL0/ SCLK SPI
CPOH0/ SDI
CPOL1/ SYNC
CPOH1/ SDO
CPOL2 CPOH2 CPOL3 /CPO0 /CPO1 /CPO2
CPOH3 /CPO3
Figure 1. Functional Block Diagram
Rev.PrL
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
AD5522 TABLE OF CONTENTS
Features..................................................................................................................... 1 Revision History...................................................................................................... 2 Specifications ........................................................................................................... 4 Table 2. TIMING Characteristics .................................................................... 8 Absolute Maximum Ratings................................................................................ 11 Thermal Resistance.......................................................................................... 11 ESD Caution ..................................................................................................... 11 Pin Configuration and Function Descriptions................................................. 12 TERMINOLOGY.................................................................................................. 15 Functional Description ........................................................................................ 16 Force Amplifier ................................................................................................ 16 Comparators ..................................................................................................... 16 Clamps ............................................................................................................... 16 Current Range selection.................................................................................. 17 High Current ranges........................................................................................ 17 Device under test ground (DUTGND) ........................................................ 17 Guard amplifer ................................................................................................. 18 Compensation Capacitors .............................................................................. 18 System Force Sense Switches.......................................................................... 19 Temperature Sensor......................................................................................... 19 Measure Output (MEASOUT) ...................................................................... 19 DAC Levels............................................................................................................. 20 Offset DAC........................................................................................................ 20 Offset and Gain registers ................................................................................ 20 Cached x2 registers .......................................................................................... 20 VREF..................................................................................................................... 21 Reference Selection.......................................................................................... 21 Calibration ........................................................................................................ 22 System Level Calibration ................................................................................ 22
Preliminary Technical Data
Force Voltage, FV ............................................................................................. 23 Force Current, FI.............................................................................................. 24 SPI INTERFACE .............................................................................................. 25 LVDS INTERFACE.......................................................................................... 25 Serial Interface Write Mode ........................................................................... 25 RESET Function............................................................................................... 25 BUSY and LOAD Function ............................................................................ 25 Register Update Rates...................................................................................... 26 Register Selection............................................................................................. 27 Write System Control Register....................................................................... 28 Write PMU Register ........................................................................................ 30 Write DAC Register ......................................................................................... 32 Read Registers................................................................................................... 34 Readback of System Control Register........................................................... 35 Readback of PMU Register............................................................................. 36 Readback of Comparator Status Register..................................................... 36 Readback of Alarm Status Register ............................................................... 37 Readback of DAC Register ............................................................................. 37 Power On Default ............................................................................................ 38 Setting up the device on power on ................................................................ 39 Changing Modes .............................................................................................. 39 Required external components ...................................................................... 40 Typical Application for the AD5522 ............................................................. 42 Outline Dimensions ............................................................................................. 43 Ordering Guide ................................................................................................ 44 Notes ....................................................................................................................... 45
REVISION HISTORY
5th Sept, Update to block diagram, timing and READ functions. .
Rev. PrL | Page 2 of 45
Preliminary Technical Data
AGND AVSS(0-4) AVDD(0-4) DVCC DGND CCOMP 0
AD5522
VREF
16 16 16
X1 REG M REG C REG
16
X2 REG *2 *2
16-Bit CLH DAC
CH0
FIN SW 1 AGND
EN
EXTFOH 0
CLH SW 3
CFF 0
REFGND
16 16 16
OFFSET DAC *6
INTERNAL RANGE SELECT (5uA, 20uA, 200uA, 2mA)
FORCE AMPLIFER
X1 REG M REG C REG
16
16-Bit FIN DAC
+ -
X2 REG *6
FOH 0 RSENSE
SW 5 SW 6 SW 7 SW 4
SW 2
16 16 16 16
X1 REG M REG C REG
X2 REG *2 *2
16-Bit CLL DAC
SW 10
OFFSET DAC BIAS TO CENTER IRANGE
CLL
EXTMEASIH 0 + SW 8
10k EXTMEASIL 0
SW 9
+
x5 or x10
MEASOUT 0
SW 12
MEASOUT MUX & GAIN x1/x0.2
TEMP SENSOR SW 11 MEASURE CURRENT IN AMP
+ -
EXTERNAL RSENSE (CURRENTS UP TO 64mA)
AGND
16 16 16
MEASVH 0 + -
*6 X1 REG M REG C REG
16
X2 REG *6
16-Bit CPH DAC
AGND
x1
+ DUTGND MEASURE VOLTAGE IN AMP
SW 13 GUARD AMP
SW 16
GUARD 0 GUARDIN 0/ DUTGND 0
DUT DUTGND
16 16 16
CPH
*6 X1 REG M REG C REG
16
CPL 16-Bit CPL DAC
+ -
SW 14 SW 15
X2 REG
COMPARATOR
+
-+
10k
AGNDx
CPOL0/ SCLK CPOH0/ SDI
CCOMP 1 MEASOUT 1 CPOL1/ SYNC CPOH1/ SDO AGND
CH1
MUX MUX
EXTFOH 1 CFF 1 FOH 1 EXTMEASIH 1 EXTMEASIL 1 MEASVH 1 GUARD 1 GUARDIN 1/DUTGND 1 SYS_SENSE SYS_FORCE EXTFOH 2 CFF 2 FOH 2 EXTMEASIH 2 EXTMEASIL 2 MEASVH 2 GUARD 2 GUARDIN 2/DUTGND 2
EN
CCOMP 2 MEASOUT 2 CPOL2/CPO0 CPOH2/CPO1 AGND
CH2
16 16 16
CCOMP 3
X1 REG M REG C REG
16
EXTFOH 3
X2 REG *2 *2 16-Bit CLH DAC
CLH SW 3
CFF 3
OFFSET DAC *6
16 16 16
CH3
FIN SW 1 FORCE AMPLIFER
INTERNAL RANGE SELECT (5uA, 20uA, 200uA, 2mA) + SW 2
X1 REG M REG C REG
16
16-Bit FIN DAC
X2 REG *6
AGND
FOH 3 RSENSE
SW 6 SW 5 SW 7 SW 4
16 16 16
X1 REG M REG C REG
16
X2 REG *2 *2
16-Bit CLL DAC
SW 10
OFFSET DAC BIAS TO CENTER IRANGE
CLL
EXTMEASIH 3
SW 8
+ +
10k EXTMEASIL 3
SW 9
x5 or x10
MEASOUT 3
SW 12
16
MEASOUT MUX & GAIN x1/x0.2
TEMP SENSOR SW 11 MEASURE CURRENT IN AMP
+ -
EXTERNAL RSENSE (CURRENTS UP TO 64mA)
AGND
MEASVH 3 + SW 16 SW 13
16 16
*6 X1 REG M REG C REG
16
X2 REG *6
16-Bit CPH DAC
AGND
x1
+ MEASURE VOLTAGE IN AMP
DUTGND + SW 14
GUARD 3
GUARD AMP
16 16 16
CPH
*6 X1 REG M REG C REG
16
16-Bit CPL DAC
CPL
SW 15
GUARDIN 3/ DUTGND 3
DUT
X2 REG
COMPARATOR
+
-+
10k
AGND
DUTGND DUTGND
16
16-Bit OFFSET DAC
16
TO ALL DAC OUTPUT AMPLIFIERS
SERIAL INTERFACE AGND
SW 15a
TO MEASOUT MUX
TEMP SENSOR CLAMP & GUARD ALARM
TMPALM
POWER ON RESET
10k
CGALM
RESET
SDO
SCLK SDI SYNC BUSY LOAD
LVDS/ CPOL3 /CPO2 SPI
CPOH3 /CPO3
Figure 2. Detailed Block Diagram
Rev. PrL | Page 3 of 45
AD5522 SPECIFICATIONS
Preliminary Technical Data
Table 1. AVDD 10V, AVSS -5V, |AVDD - AVSS| 20V and 33V, DVCC = 2.3V to 5.25V, VREF=5V, Gain (m), Offset (c) and DAC Offset registers at default values (TJ = +25 to +90oC, max specs unless otherwise noted.)
Parameter FORCE VOLTAGE FOH Output Voltage Range EXTFOH Output Voltage Range Output Voltage Span Offset Error Offset Error Tempco2 Gain Error Gain Error Tempco2 Linearity Error Short Circuit Current Limit2 MEASURE CURRENT Offset Error Offset Error Tempco2 Gain Error Gain Error Tempco2 Linearity Error Output Voltage Span2 CM Error Measure Current Ranges Min AVSS+4 AVSS+3 -100 100 -0.5 10 -0.02 -120 -10 -1 10 -1 25 -0.01 -0.005 5 20 200 2 Up to 64 FORCE CURRENT Voltage Compliance, FOH Voltage Compliance, EXTFOH Offset Error Offset Error Tempco2 Gain Error Gain Error Tempco2 Linearity Error CM Error Force Current Ranges -0.5 25 -0.02 -0.005 5 20 200 2 Up to 64 MEASURE VOLTAGE Measure Voltage Range Offset Error Offset Error Tempco2 Gain Error Gain Error Tempco2 Linearity Error AVSS+4 -10 10 -0.5 10 -0.01 0.01 0.5 AVDD-4 10 0.02 0.005 AVSS+4 AVSS+3 -2 10 0.5 AVDD-4 AVDD-3 2 0.01 22.5 0.005 1 0.02 120 10 1 0.5 Typ1 Max AVDD-4 AVDD-3 22.5 100 Units V V V mV V/ oC % ppm/ oC % FSR mA mA % V/ oC % ppm/ oC % FSCR V %FSCR/V A A A mA mA V V %FSCR ppm FS/ o C % ppm/ oC % FSCR %FSCR/V A A A mA mA V V mV V/ oC % FSR ppm/ oC % FSR FSR = Fullscale Range. 10 V range, Gain and offset errors calibrated out. On 64mA range. In all other ranges. MEASURE = (IDUT X RSENSE x GAIN) V(Rsense)= 1V Instrumentation Amp Gain = 5 or 10 Offset and Gain errors calibrated out % of FS Change at measure output per V change in DUT voltage Set using internal sense resistor Set using internal sense resistor Set using internal sense resistor Set using internal sense resistor Set using external sense resistor, internal amplifier can drive to 64mA Test Conditions/Comments All current ranges from FOH at full scale current. Includes 1V dropped across sense resistor External high current range at full scale current. Does not include 1V dropped across sense resistor
Gain = 1
% of FS Change at measure output per V change in DUT voltage Set using internal sense resistor, 200k Set using internal sense resistor, 50k Set using internal sense resistor, 5k Set using internal sense resistor, 500 Set using external sense resistor, internal amplifier can drive to 64mA
Gain = 1
Rev. PrL | Page 4 of 45
Preliminary Technical Data
Parameter COMPARATOR Comparator Span Offset Error Propagation delay2 VOLTAGE CLAMPS Clamp Span Positive Clamp Accuracy Negative Clamp Accuracy Recovery Time2 Activation Time2 CURRENT CLAMPS Clamp Accuracy Recovery Time2 Activation Time2 FOH, EXTFOH, EXTMEASIL, EXTMEASIH, CFF Pin Capacitance2 Leakage Current Leakage Current Tempco2 MEASVH Pin Capacitance2 Leakage/Bias Current Leakage Current Tempco2 SYS_SENSE Pin Capacitance2 SYS_SENSE Impedance Leakage Current Leakage Current Tempco2 SYS_FORCE Pin Capacitance2 SYS_FORCE Impedance Leakage Current Leakage Current Tempco2 COMBINED LEAKAGE at DUT Leakage Current Leakage Current Tempco2 DUTGND Voltage Range Leakage Current MEASURE OUTPUT (MEASOUT) Measure Output Voltage Span Measure Pin output Impedance Output leakage current Output Capacitance2 Short Circuit Current2 MEASOUT enable time MEASOUT disable time MEASOUT MI to MV switching time GUARD OUTPUT Guard Output Voltage Span Guard Output Offset Short Circuit Current2 Load Capacitance2 Guard Output Impedance Slew Rate2 -15 0.5 -500 -1 500 1 22.5 100 3 15 10 TBD TBD TBD 22.5 10 10 50 100 3 15 nA nA/ oC typ mV A V nA pF mA ns ns ns V mV mA nF V/s With respect to AGND Software Programmable output range With SW12 off Min Typ1 Max 22.5 10 TBD 22.5 150 -150 TBD TBD Prog'd Clamp value TBD TBD TBD TBD Programmed Clamp value +15 TBD TBD Units V mV s V mV mV s s % of FSC range s s Test Conditions/Comments
AD5522
-10 1
Clamp current scales with selected range
3 -3 0.1 3 -3 0.1 3 1 -3 0.1 3 60 -3 0.1
TBD 3
pF nA nA/ oC pF nA nA/ oC
On or off switch leakage
TBD 3
SYS_Sense Connected, Force Amplifier Inhibited TBD 1.3 3 pF k nA nA/ oC SYS_Force Connected, Force Amplifier Inhibited TBD 80 3 pF nA nA/ oC Includes FOH, MEASVH, SYS_SENSE, SYS_FORCE, EXTMEASIL
-3 -10 TBD TBD TBD
Closing SW12 Opening SW12
-10 -10
CLOAD = TBD pf
Rev. PrL | Page 5 of 45
AD5522
Parameter FORCE AMPLIFIER Slew Rate2 Gain Bandwidth2 Max stable load Capacitance2 FV SETTLING TIME TO 0.05% OF FSVR 64mA Range2 2mA range2 200A range2 20A range2 5A range2 MI SETTLING TIME TO 0.05% OF FSCR 64mA Range2 2mA range2 200A range2 20A range2 5A range2 FI SETTLING TIME TO 0.05% OF FSCR 64mA Range2 2mA range2 200A range2 20A range2 5A range2 MV SETTLING TIME TO .05% OF FSVR 64mA Range2 2mA range2 200A range2 20A range2 5A range2 DAC SPECIFICATIONS Resolution Voltage Output Span2 Differential Nonlinearity2 COMPARATOR DAC DYNAMIC SPECIFICATIONS Output Voltage Settling Time2 Slew Rate2 Digital-to-Analog Glitch Energy2 Glitch Impulse Peak Amplitude2 REFERENCE INPUT VREF DC Input Impedance VREF Input Current VREF Range DIE TEMPERATURE SENSOR Accuracy Output Voltage at 25C Output Scale Factor Output Voltage Range INTERACTION & CROSSTALK Crosstalk (VM) 2 Min Typ1 0.4 1 10,000 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 30 30 80 680 3000 TBD TBD TBD TBD TBD 40 40 40 80 300 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 16 22.5 1 Max Units V/us MHz pF s s s s s s s s s s s s s s s s s s s s Bits V LSB
Preliminary Technical Data
Test Conditions/Comments Ccomp=100pF, Cff=220pF, Cload=200pF Ccomp=100pF, Cff=220pF, Cload=200pF CCOMP = 100pF. Larger Load cap requires larger CCOMP FS step Ccomp=100pF, Cff=220pF, Cload=200pF Ccomp=100pF, Cff=220pF, Cload=200pF Ccomp=100pF, Cff=220pF, Cload=200pF Ccomp=100pF, Cff=220pF, Cload=200pF Ccomp=100pF, Cff=220pF, Cload=200pF FS step Ccomp=100pF, Cff=220pF, Cload=200pF Ccomp=100pF, Cff=220pF, Cload=200pF Ccomp=100pF, Cff=220pF, Cload=200pF Ccomp=100pF, Cff=220pF, Cload=200pF Ccomp=100pF, Cff=220pF, Cload=200pF FS step Ccomp=100pF, Cload=200pF Ccomp=100pF, Cload=200pF Ccomp=100pF, Cload=200pF Ccomp=100pF, Cload=200pF Ccomp=100pF, Cload=200pF FS step Ccomp=100pF, Cload=200pF Ccomp=100pF, Cload=200pF Ccomp=100pF, Cload=200pF Ccomp=100pF, Cload=200pF Ccomp=100pF, Cload=200pF
-1
VREF=5V, within a range of -16.25 to 22.5V Guaranteed monotonic by design over temperature.
1.5 5 20 15 1 -10 2 7 1.5 5 0 -0.01 3 0.01
s V/s nV-s mV M A V C V mV/C V % FSR
1V change to 1 LSB.
10 5
Typically 100 M. Per input. Typically 30 nA.
Crosstalk (MI) 2
-0.01
0.01
% FSR
Crosstalk within a channel2
0.5
mV
All channels in FIMV mode, measure the voltage for one channel in the highest current force range, once when all three other channels are at FI = 0mA and once when they are at 2mA All channels in FVMI mode, measure the current for one channel in the lowest current measure range, once when all three other channels are at FV = -10V and once when they are at +10V All channels in FVMI mode, one channel at midscale, measure the current for one channel in the lowest current range, for a change in comparator or clamp DAC
Rev. PrL | Page 6 of 45
Preliminary Technical Data
Parameter Shorted DUT Crosstalk2 SPI INTERFACE LOGIC LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance2 CMOS LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage Tristate leakage current Output Capacitance2 OPEN DRAIN LOGIC OUTPUTS VOL, Output Low Voltage Output Capacitance2 LVDS INTERFACE LOGIC LOGIC INPUTS - Reduced Range Link Input Voltage Range Input Differential Threshold External Termination Resistance Differential Input Voltage LOGIC OUTPUTS - Reduced Range Link Output Offset Voltage Output Differential Voltage NOISE PERFORMANCE NSD of Measure Voltage In-Amp NSD of Measure Current In-Amp NSD of Force Amplifier POWER SUPPLIES AVDD AVSS DVCC AIDD AISS DICC Max Power Dissipation2 Power Supply Sensitivity2 Forced Voltage/AVDD Forced Voltage/AVSS Measured Current/AVDD Measured Current/AVSS Forced Current/AVDD Forced Current/AVSS Measured Voltage/AVDD Measured Voltage/AVSS Forced Voltage/DVCC Measured Current/DVCC Forced Voltage/DVCC Measured Current/DVCC
1 2
AD5522
Typ1 TBD Max TBD Units Test Conditions/Comments levels for that PMU. S/C applied to one PMU channel, measure effect on other channels.
Min
1.7/2.0 -1 0.7/0.8 1 10
V V A pF V V A pF V pF
(2.3 to 2.7)/(2.7 to 5.25V) Jedec Compliant Input Levels (2.3 to 2.7)/(2.7 to 5.25V) Jedec Compliant Input Levels
SDO, CPOX DVCC - 0.4 -1 0.4 1 10 0.4 10 IOL = 500 A
BUSY, TMPALM, CGALM IOL = 500 A, CL = 50pF, RPULLUP = 1k
875 -100 80 100
100
1575 100 120
mV mV mV mV mV nV/Hz nV/Hz nV/Hz @ 1kHz, measured at MEASOUT @ 1kHz, measured at MEASOUT @ 1kHz, measured at FOH | AVDD - AVSS| 33V
1200 400 TBD TBD TBD 10 -5 2.3 28 -23 5.25 25 25 3 7 -75 -75 -75 -75 -75 -75 -75 -75 -90 -90 -90 -90
V V V mA mA mA W dB dB dB dB dB dB dB dB dB dB dB dB
Excluding Load Conditions Excluding Load Conditions
From DC to 1kHz
Typical specifications are at 25C and nominal supply, 15.25V, unless otherwise noted. Guaranteed by design and characterization, not production tested.
FV = Force Voltage, FI = Force Current, MV = Measure Voltage, MI = Measure Current FSR = Full Scale Range, FSCR = Full Scale Current Range, FS = Full Scale. Specifications subject to change without notice.
Rev. PrL | Page 7 of 45
AD5522
TABLE 2. TIMING CHARACTERISTICS AVDD 10V, AVSS -5V, |AVDD - AVSS| 20V and 33V, DVCC = 2.3V to 5.25V, VREF=5V
(TJ = +25 to +90oC, max specs unless otherwise noted.)
SPI INTERFACE (Figure 5 and Figure 6) Parameter1, 2, 3 Limit at TMIN, TMAX t1 20 t2 8 t3 8 t4 10 t5 t6 t7 t8 t93 t10 t11 t12 t13 t14 t15 t16 t17 t18 t194 15 5 5 4.5 30 1.2 20 20 150 0 100 10 300 100 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns max s max ns min ns min ns min ns min ns max ns min s max ns min ns max ns min Unit ns min ns min ns min ns min ns min ns min ns min ns min
Preliminary Technical Data
Description SCLK Cycle Time. SCLK High Time. SCLK Low Time. SYNC Falling Edge to SCLK Falling Edge Setup Time. Minimum SYNC High Time. 29th SCLK Falling Edge to SYNC Rising Edge. Data Setup Time. Data Hold Time. SYNC Rising Edge to BUSY Falling Edge. BUSY Pulse Width Low 29th SLCK Falling EDGE to LOAD Falling Edge LOAD pulse width low BUSY rising edge to FOH Output Response time BUSY rising edge to LOAD falling edge LOAD rising edge to FOH Output Response time RESET Pulse Width Low. RESET Time Indicated by BUSY Low. Minimum SYNC High Time in Readback Mode. SCLK Rising Edge to SDO Valid. Single channel write time Description SCLK Cycle Time. SCLK Pulse Width High and Low Time. SYNC to SCLK Setup Time. Data Setup Time. Data Hold Time. SCLK to SYNC Hold Time. SCLK Rising Edge to SDO Valid. SYNC high time
25 595 LVDS INTERFACE (Figure 7) Parameter1, 2, 3 Limit at TMIN, TMAX t1 10 t2 4 t3 2 t4 t5 t6 t7 t8
1 2 3
2 2 2 TBD TBD
Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V. See Figure 5 and Figure 6 4 This is measured with circuit the load circuit of Figure 4
V CC
200A IOL
RL TO OUTPUT PIN
2.2k
TO OUTPUT PIN
CL
50pF 200A IOL
V OH (min) - V OL (max) 2
V OL CL 50pF
Figure 3.. Load Circuit forCGALM, TMPALM
Figure 4. Load Circuit for SDO, BUSY Timing Diagram
Rev. PrL | Page 8 of 45
Preliminary Technical Data
t1 SCLK 1 2 t3 t4 t6 SYNC t5 t7 t8 SDI DB28 DB0 t2 29 24
AD5522
t9 t10 BUSY
t11 LOAD1 FOH1
t12
t13 t14 t12
LOAD2
FOH2
t15
t16 RESET
BUSY
1LOAD ACTIVE 2 LOAD ACTIVE
t17 DURING BUSY AFTER BUSY
Figure 5. SPI Write Timing (Write word contains 29 bits)
SCLK
29 t19 t18
58
SYNC
SDI
DB28
DB0
DB23/ DB28
DB0
INPUT WORD SPECIFIES REGISTER TO BE READ SDO DB23/ DB28
NOP CONDITION
DB0
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
Figure 6. SPI Read Timing (Readback word contains 24 bits and can be clocked out with a minimum of 24 clock edges)
Rev. PrL | Page 9 of 45
AD5522
t8 SYNC SYNC t3 SCLK SCLK SDI MSB D28 t2 LSB D0 SDI t5 SDO SDO UNDEFINED t7 MSB DB23/ DB28 t4 MSB D23/D28 t1
Preliminary Technical Data
t6
LSB D0
LSB DB0
SELECTED REGISTER DATA CLOCK OUT
Figure 7. LVDS Read and Write Timing, (Readback word contains 24 bits and can be clocked out with a minimum of 24 clock edges)
Rev. PrL | Page 10 of 45
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 3. AD5522 Absolute Maximum Ratings
Parameter Supply Voltage AVDD to AVSS AVDD to AGND AVSS to AGND VREF to AGND DUTGND, REFGND, AGND DVCC to DGND Digital Inputs to DGND Analog Inputs to AGND Storage Temperature Operating Junction Temperature Reflow Soldering Peak Temperature Time at Peak Temperature Junction Temperature Rating 34V -0.3V to 34V 0.3V to -34V -0.3 V, +7V AVDD +0.3V to AVSS -0.3V - 0.3V to 7V - 0.3V to DVCC +0.3V AVSS - 0.3V to AVDD +0.3V -65C to +125C +25 to +90C 230C 10s to 40s 150C max
AD5522
THERMAL RESISTANCE3
Thermal resistance values are specified for the worst-case conditions, i.e., specified for device soldered in circuit board for surface mount packages. Table 4. Thermal Resistance (JEDEC 4 layer (1S2P) board)
Air Flow (LFPM) TQFP Exposed Pad Down TQFP Exposed Pad Up JA JC JA JC 0 22.3 0.3 TBD 4.8 TBD TBD 200 17.2 500 15.1 Unit C/W C/W C/W C/W
Table 5. Thermal Resistance (JEDEC 4 layer (1S2P) board with cooling plate4 at 45C, natural convection at 55C ambient)
Package Thermals TQFP Exposed Pad Down TQFP Exposed Pad Up
3 4
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
JA 5.4 3.0
JA 4.8 0.3
Unit C/W C/W
Simulated Thermal information. Assumes perfect thermal contact between cooling plate and exposed paddle
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrL | Page 11 of 45
AD5522 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SYS_FORCE SYS_SENSE MEASOUT1 MEASOUT0 MEASOUT2 MEASOUT3 EXTFOH0 DUTGND 76 75 80 79 77 73 72 71 68 67 64 63 70 78 74 69 65 66 62
Preliminary Technical Data
AVDD CFF0 CCOMP0 EXTMEASIH0 EXTMEASIL0 FOH0 GUARD0 GUARDIN0 /DUTGND0 MEASVH0 AGND AGND MEASVH2 GUARDIN2 /DUTGND2 GUARD2 FOH2 EXTMEASIL2 EXTMEASIH2 CCOMP2 CFF2 AVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
61
EXTFOH1
SPI/LVDS
TMPALM
RESET
REFGND
CGALM
AVDD
AGND
AVSS
VREF
AVSS
AVSS
60 59 58 57 56 55 54 53
AVDD CFF1 CCOMP1 EXTMEASIH1 EXTMEASIL1 FOH1 GUARD1 GUARDIN1 /DUTGND1 MEASVH1 AGND AGND MEASVH3 GUARDIN3 /DUTGND3 GUARD3 FOH3 EXTMEASIL3 EXTMEASIH3 CCOMP3 CFF3 AVDD
AD5522
TOP VIEW EXPOSED PAD ON BOTTOM (Not to Scale)
52 51 50 49 48 47 46 45 44 43 42 41
CPOL0/SCLK
SYNC
DGND
DVCC
CPOH3/CPO3
EXTFOH2
CPOL1/SYNC
CPOH2/CPO1
CPOH1/SDO
CPOH0/SDI
CPOL2/CPO0
CPOL3/CPO2
Figure 8. Pin Configuration (Exposed Pad on bottom of package)
Table 6. Pin Function Descriptions
Pin No. Bottom Pin No. Top Mnemonic Exposed Pad Description The exposed pad is electrically connected to AVSS. TQFP with exposed pad on BOTTOM: For enhanced thermal, electrical and board level performance, the exposed paddle on the bottom of the package should be soldered to a corresponding thermal land paddle on the PCB. Negative analog supply voltage Positive analog supply voltage Active low logic input used for synchronizing updates within one device or across a group of devices. If synchronization is not required, LOAD may be tied low and updates to DAC channels or PMU modes will happen as they are presented to the device. See the BUSY and LOAD FUNCTIONS section for detailed information. Digital supply voltage Analog ground, reference points for force and measure circuitry Digital ground reference point. Open Drain active low input/output indicating the status of interface. Clock input, active falling edge Comparator output low in SPI mode and SCLK in LVDS interface mode Comparator output high in SPI mode and SDI in LVDS interface mode Serial data input Frame sync, active low Comparator output low in SPI mode and SYNC in LVDS interface mode Comparator output high in SPI mode and SDO in LVDS interface mode
Rev. PrL | Page 12 of 45
22, 39, 62, 67, 79, 1, 20, 41, 60, 74 33
2, 14, 19, 42,59, 7, 21, 40, 61, 80 48
AVSS(0-4) AVDD(0-4) LOAD
34 10, 11, 50, 51, 69 30 23 24 25 26 27 28 29 31
47 12, 30, 31, 70, 71 51 58 57 56 55 54 53 52 50
DVCC AGND DGND BUSY SCLK CPOL0/ SCLK CPOH0/ SDI SDI SYNC CPOL1/ SYNC CPOH1/SDO
EXTFOH3
BUSY
SCLK
SDO
SDI
LOAD
AVSS
AVSS
Preliminary Technical Data
32 35 36 37 38 66, 65, 64, 63 68 70 71 72 75 49 46 45 44 43 15, 16, 17, 18 13 11 10 9 6 SDO CPOL2/CPO0 CPOH2/CPO1 CPOL3/CPO2 CPOH3/CPO3 MEASOUT(0-3) SYS_FORCE SYS_SENSE REFGND VREF SPI/LVDS
AD5522
Serial data out, for readback and diagnostic purposes Comparator output Low, comparator window in LVDS interface mode Comparator output Low, comparator window in LVDS interface mode Comparator output Low, comparator window in LVDS interface mode Comparator output Low, comparator window in LVDS interface mode Multiplexed DUT voltage/Current sense output/temperature sensor voltage per channel, referenced to AGND. External FORCE signal input, enables connection of system PMU. External SENSE signal output, enables connection of system PMU. Accurate analog reference input ground. Reference Input for DAC channels, 5V for specified performance. Interface select pin. Logic low selects SPI interface compatible mode, logic high selects LVDS interface mode. In LVDS mode the CPOH(0-3) pins default to differential interface pins. CGALM is an open drain pin providing shared Alarm information for Guard amplifier and Clamp circuitry. By default, this output pin is disabled. The System Control Register allows user to enable this function and to set the open drain output as a latched output, or to configure either the Guard or Clamp function or both flagging the alarm pin. When this pin flags an alarm, the origins of the alarm may be determined by reading back the Alarm Status Register. Two flags per channel in this word (one latched, one unlatched) indicate which function caused the alarm and if the alarm is still present. The function of this pin is to flag a Temperature Alarm. It is a latched active low open drain output indicating the junction temperature has exceeded either the programmed or default (130degC) temperature setting. Two flags in the Alarm Status Register (one latched, one unlatched) indicate if the temperature has dropped below 130degC or still above. User action is required to clear this latched alarm flag, by writing to the "CLEAR" bit in any of the PMU registers. Active low, level sensitive input used to reset all internal nodes on the device to their power-on reset value. Compensation capacitor Input per channel. See section on compensation capacitors.. External capacitor optimizing the stability performance of the force amplifier (per channel).. See section on Compensation Capacitors Per channel, Force output for high current range. Use external resistor here for current range up to 64mA. Per channel force output for all other ranges. Per channel sense input (high sense) for high current range. Per channel sense input (Low sense) for high current range. Per channel DUT voltage sense input (high sense) DUT voltage sense input (low sense). By default, DUTGND is shared between all four PMU channels. If user requires a DUTGND input per channel, the GUARDIN (0-3)/DUTGND(0-3) pin may be configured to be a DUTGND input per each PMU channel. Guard output drive. This pin has dual functionality; it may be either a Guard input per channel or DUTGND per channel. Its function is determined via the serial interface. The power on default is GUARDIN, where it functions as the input to the Guard Amplifier. Alternatively, it may be configured to be a DUTGND input per channel. If selected as DUTGND via the interface, it now provides a DUTGND per Channel function and the input to the Guard amplifier is internally connected to MEASVH. See section on Guard Amplifier
76
5
CGALM
77
4
TMPALM
78 3, 18, 43, 58 2, 19, 42, 59 80, 21, 40, 61 6, 15, 46, 55 4, 17, 44, 57 5, 16, 45, 56 9, 12, 49, 52 73
3 78, 63, 38, 23 79, 62, 39, 22 1, 60, 41, 20 75, 66, 35, 26 77, 64, 37, 24 76, 65, 36, 25 72, 69, 32, 29 8
RESET CCOMP(0-3) CFF (0-3) EXTFOH(0-3) FOH(0-3) EXTMEASIH(0-3) EXTMEASIL(0-3) MEASVH(0-3) DUTGND
7, 14 , 47, 54 8, 13, 48, 53
74, 67, 34, 27 73, 68, 33, 28
GUARD (0-3)
GUARDIN(0-3) /DUTGND(0-3)
Rev. PrL | Page 13 of 45
AD5522
EXTMEASIH0 EXTMEASIL2 GUARDIN0 DUTGND0 MEASVH0 EXTMEASIH2 EXTMEASIL0 GUARDIN2 \DUTGND2 GUARD2 MEASVH2 CCOMP0 CCOMP2 GUARD0 AGND AGND AVDD FOH0 FOH2 CFF0 CFF2 62
Preliminary Technical Data
AVDD 61
80
79
77
76
75
73
72
71
69
68
67
65
78
74
70
EXTFOH0 AVSS RESET TMPALM CGALM SPI/LVDS AVDD DUTGND VREF REFGND SYS_SENSE AGND SYS_FORCE AVSS MEASOUT0 MEASOUT1 MEASOUT2 MEASOUT3 AVSS EXTFOH1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
37 38 39 27 29 28 26 30 25 31 32 21 22 23 24 33 34 35 36 40
66
64
63
60 59 58 57 56 55 54 53
EXTFOH2 AVSS BUSY SCLK CPOL0/SCLK CPOH0/SDI SDI SYNC CPOL1/SYNC DGND CPOH1/SDO SDO LOAD DVCC CPOL2/CPO0 CPOH2/CPO1 CPOL3/CPO2 CPOH3/CPO3 AVSS EXTFOH3
AD5522
TOP VIEW EXPOSED PAD ON TOP (Not to Scale)
52 51 50 49 48 47 46 45 44 43 42 41
CFF1
GUARDIN1/ DUTGND1
GUARDIN3/ DUTGND3
CCOMP1
MEASVH1
MEASVH3
EXTMEASIL1
EXTMEASIL3
CCOMP3
AGND
AGND
AVDD
CFF3
EXTMEASIH1
Figure 9. Pin Configuration (Exposed Pad on Top of package)
Rev. PrL | Page 14 of 45
EXTMEASIH3
GUARD1
GUARD3
FOH3
AVDD
FOH1
Preliminary Technical Data TERMINOLOGY
Offset Error Offset error is a measure of the difference between actual and ideal voltage expressed in mV. Gain Error Gain error is the difference between full-scale error and zero-scale error. It is expressed in %. Gain Error = Full-Scale Error - Zero-Scale Error Linearity Error Relative accuracy, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the full-scale range. It is measured after adjusting for offset error and gain error and is expressed in % FSR. CM Error Common Mode Error is the error at the output of the amplifier due to the common mode input voltage. It is expressed in % of FSR/V. Clamp Accuracy Clamp accuracy is a measure of where the clamps begin to function fully and limit the clamped voltage or current. Leakage Current Current measured at an output pin, when that function is off or high impedance. Pin Capacitance Capacitance measured at a pin when that function is off or high impedance. Slew Rate The rate of change of output voltage, expressed in V/s.
AD5522
DAC SPECIFIC TERMS Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1LSB maximum ensures monotonicity. Output Voltage Settling Time The amount of time it takes for the output of a DAC to settle to a specified level for a full-scale input change. Digital-to-Analog Glitch Energy The amount of energy injected into the analog output at the major code transition. The area of the glitch in is specified in nV-s. It is measured by toggling the DAC register data between 0x1FFF and 0x2000. Digital Crosstalk The glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter is defined as the digital crosstalk and is specified in nV-s. Digital Feedthrough When the device is not selected, high frequency logic activity on the device's digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins. It can also be coupled along the supply and ground lines. This noise is digital feedthrough.
Rev. PrL | Page 15 of 45
AD5522 FUNCTIONAL DESCRIPTION
The AD5522 is a highly integrated quad per pin parametric measurement unit (PPMU) for use in semiconductor automatic test equipment. It contains programmable modes to force a pin voltage and measure the corresponding current (FVMI), force current measure voltage (FIMV), force current measure current (FIMI), force voltage measure voltage (FVMV) and force nothing measure voltage (FNMV) or measure current (FNMI). The PPMU can force or measure a voltage range of 22.5 V. It can force or measure currents ranging up to 64mA per channel using the internal amplifier, while the addition of an external amplifier enables higher current ranges. On Chip are all the DAC levels required for each PMU channel.
Preliminary Technical Data
comparator output available CPO (0-3) provides information on whether the measured voltage or current is inside or outside the set CPH and CPL window. Information of whether the measurement was high or low is available via the serial interfaces (Comparator Status Register). Table 8. Comparator Output Function using LVDS interface
TEST CONDITION
CPL < VDUT And IDUT < CPH CPL > VDUT or IDUT > CPH CPO Output 1 0
CLAMPS
Current and voltage clamps are included on chip per PMU channel. They protect the DUT in the event of an open or a short. Internal DAC levels set the CLL and CLH (low and high) levels and the clamps work to limit the force amplifier in the event of a voltage or current at the DUT exceeding the set levels. The clamps also function to protect the DUT when a transient voltage or current spike occurs when changing to a different operating mode or when programming the device to a different current range. The voltage clamps are active while forcing current and the current clamps are active while forcing voltage. By default, the current clamps are off. Simply set them up via the status register through the serial interface. If a clamp level has been hit, this will be flagged via the CGALM open drain output and the resulting alarm information may be read back via the SPI or LVDS interface. CLL should never be greater than CLH.
FORCE AMPLIFIER
The force amplifier drives the analog output FOH, which drives a programmed current or voltage to the DUT (device under test). Headroom and footroom requirements for this amplifier is 3V on either end. An additional 1V is dropped across the sense resistor when maximum current is flowing through it. This amplifier is designed to drive DUT capacitances up to 10nF, with a compensation value of 100pF. Larger DUT capacitive load will require larger compensation capacitances. Local feedback ensures the amplifiers are stable when disabled. A disabled channel reduces power consumption by 2.5mA/channel.
COMPARATORS
Per channel, the DUT measured value is monitored by two comparators configured as window comparators. Internal DAC levels set the CPL and CPH (low and high) threshold values. There are no restrictions on the voltage settings of the comparator high and lows. CPL going higher than CPH is not a useful operation; however, it will not cause any problems to the device. CPOL and CPOH are continuous time comparator outputs. Table 7. Comparator Output Function
TEST CONDITION VDUT or IDUT > CPH VDUT or IDUT < CPH VDUT or IDUT > CPL VDUT or IDUT < CPL CPH > VDUT or IDUT > CPL 1 0 1 1 CPOL CPOH 0 1
When using SPI interface, full comparator functionality is available. When using the LVDS interface, the comparator function is limited to one output per comparator, due to the large pin count requirement of the LVDS interface. In this case,
Rev. PrL | Page 16 of 45
Preliminary Technical Data
CURRENT RANGE SELECTION
Integrated thin film resistors minimize external components and allow easy selection of current ranges from 5 A (200k), 20A (50k), 200A (5k) and 2mA (500). Per channel, one current range up to 64mA may be accommodated by connecting an external sense resistor. For current ranges in excess of 64mA, it is recommended an external amplifier be used. For the suggested current ranges, the maximum voltage drop across the sense resistors is 1V, however, to allow for correction of errors, there is some over range available in the current ranges. The full-scale voltage range that can be loaded to the DAC is 11.5V; the forced current may be calculated as follows:
FIN
DAC
AD5522
EN
HIGH CURRENT BUFFER EXTFOH CFF
INTERNAL RANGE SELECT (5uA, 20uA, 200uA, 2mA) + Rsense FOH
OFFSET DAC BIAS TO CENTER IRANGE
EXTMEASIH + +
x5 or x10
10k + EXTMEASIL
Rsense
MEASOUT
x1/x0.2
-
AGND
MEASVH + +
x1
DUT DUTGND + -
-
Figure 10. Addition of high current amplifier for wider current range(>64mA)
DEVICE UNDER TEST GROUND (DUTGND)
By default, there is one DUTGND input available for all four PMU channels. In some applications of a PMU, it is necessary that each channel operate from its own DUTGND level. There is a shared pin in the form of the GUARDIN(0-3)/DUTGND(03) which may be shared as either the input to the GUARD amplifier (GUARDIN), or as a DUTGND per channel function. This should be configured through the serial interface on power on as per required operation. The default connection is SW13b and SW14b. When configured as DUTGND per channel, this multifunction pin is no longer connected to the input of the guard amplifier, it is instead connected to the low end of the instrumentation amplifier (SW14a), and the input of the Guard amplifier is not connected internally to MEASVH (SW13a).
MEASVH (0-3)
VFIN FI = RSENSE x Gain
Where: FI = Forced Current VFIN = Voltage of the FIN DAC, See VOUT for DAC levels. RSENSE = Selected Sense Resistor Gain of Current Measure Instrumentation amplifier, it may be set (via the serial interface) to 5 or 10. Using the 5k sense resistor and ISENSE gain of 10, the maximum current range possible is 225A. Similarly for the other current ranges, there is an over range of 12.5% to allow for correction. Also, the forced current range will only be the quoted full scale range with an applied reference of 5V or 2.5V (with ISENSE AMP gain = 5). The ISENSE amplifier is biased by the Offset DAC output voltage, in such as way as to center the Measure current output irrespective of the voltage span used. When using the EXTFOHx outputs for current ranges up to 64mA, there is no switch in series with the EXTFOHx line, ensuring minimum capacitance presented at the output of the force amplifier. This is also an important feature if using a Pin electronics driver to provide high current ranges.
DUT
+ AGNDx
x1
a SW 13 b
GUARD AMP
SW 16
+ MEASURE VOLTAGE IN AMP
GUARD (0-3)
GUARDIN (0-3)/ DUTGND (0-3)
+ -
a SW 14 b
a
DUTGND
Figure 11. Using the DUTGND per channel Feature
HIGH CURRENT RANGES
With the use of an external high current amplifier, one high current range in excess of 64mA is possible. The high current amplifier simply buffers the force output and provides the drive for the required current.
Rev. PrL | Page 17 of 45
AD5522
GUARD AMPLIFER
A Guard amplifier allows the user to bootstrap the shield of the cable to the voltage applied to the DUT, ensuring minimal drops across the cable. This is particularly important for measurements requiring a high degree of accuracy and in leakage current testing. If not required, all four Guard Amplifiers may be disabled via the serial interface (through the System Control Register), this decreases the power consumption by 400uA per channel. As described in the DUTGND section, the GUARDIN(0-3) /DUTGND(0-3) is a shared pin. It can function either as a guard amplifier input per channel or as a DUTGND input per channel as required by the end application. Refer to Figure 11. A Guard alarm event occurs when the guard output moves more than 100mV away from the Guard input voltage for more than 200s. In the event this happens, this will be flagged via the CGALM open drain output. As the guard and clamp alarm functions share the same alarm outputCGALM, the alarm information (alarm trigger and alarm channel) is available via the serial interface (ALARM STATUS REGISTER). Alternatively, the serial interfaces allow the user to setup the CGALM output to flag either the clamp status or the guard status. By default, this open drain alarm pin is an unlatched output, but may be set to a latched output via the serial interface, System Control Register.
Preliminary Technical Data
COMPENSATION CAPACITORS
Each channel requires an external compensation capacitor (CCOMP) to ensure stability into the maximum load capacitance while ensuring settling time is optimized. In addition, one CFF pin is provided to further optimize stability and settling time performance when in Force voltage mode. When changing from Force current to force voltage mode, the switch connecting CFF capacitor is automatically closed. While the force amplifier is designed to drive load capacitances up to 10nF, using larger compensation capacitor values, it is possible to drive larger load at the expense of an increase in settling time. If a wide range of load capacitance must be driven, then an external multiplexer connected to the CCOMP pin will allow optimization of settling time versus stability. The series resistance of a switch placed on CCOMP, should typically be <50. Similarly, connecting the CFF node to a multiplexer externally, would cater for a wide range of CDUT in Force Voltage mode. The series resistance of the multiplexer used should be such that:
1 2 RON x CDUT > 100kHz
Table 9. Suggested Compensation Capacitor Selection
CLOAD 1nF 10nF 100nF CCOMP 100pF 100pF CLOAD/100 CFF 220pF 1nF CLOAD/10
Rev. PrL | Page 18 of 45
Preliminary Technical Data
SYSTEM FORCE SENSE SWITCHES
Each channel has switches to allow connection of the force (FOHx) and sense (MEASVHx) lines to a central PMU for calibration purposes. There is one set of SYS_FORCE and SYS_SENSE pins per device.
AD5522
MEASURE OUTPUT (MEASOUT)
The measured DUT voltage or current (voltage representation of DUT current) is available on MEASOUT (0-3) with respect to AGND. The default MEASOUT range is the forced voltage range for voltage measure and current measure (nominally 11.25V, depends on reference voltage and offset DAC) and includes some over range to allow for offset correction. The serial interface allows the user to select another MEASOUT range of VREF to AGND, allowing for a smaller input range ADC to be used. Each PMU channel MEASOUT line may be made high impedance via the serial interface. When using low supply voltages, ensure that there is sufficient headroom and footroom for the required force voltage range. The Offset DAC also directly offsets the MEASURE output voltage level, but only when GAIN1 = 0.
TEMPERATURE SENSOR
An on board temperature sensor monitors temperatures and in the event of the temperature exceeding a factory defined value, (130C) or a user programmable value, the device will protect itself by shutting down all channels and will flag an alarm through the latched open drain TMPALM pin. Alarm status may be readback from the Alarm Status Register or the PMU registers where latched and unlatched bits tell if an alarm has occurred and whether the temperature has dropped below the set alarm temperature.
Table 10. MEASOUT Output Ranges
MEASOUT Function MV MI GAIN0 = "0" GAIN0 = "1" CURRENT MEAS GAIN = 10 CURRENT MEAS GAIN = 5 GAIN1 = "0"VREF = 5V MEASOUT Gain = 1 VDUT (up to 11.25V) VRSENSE X 10 = up to 11.25V VRSENSE X 5 = up to 5.625 GAIN1 = "1" MEASOUT Gain = 1/5
0 to 4.5VREF 5
0 to 4.5V 0 to 2.25V
Rev. PrL | Page 19 of 45
AD5522 DAC LEVELS
Each channel contains five dedicated DAC levels : one for the force amplifier, one each for the clamp high and low levels and one each for the comparator high and low levels. The architecture of a single DAC channel consists of a 16-bit resistor-string DAC followed by an output buffer amplifier. This resistor-string architecture guarantees DAC monotonicity. The 16-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. The transfer function for DAC outputs is:
DACCODE OFFSETDAC CODE VOUT = 4.5VREF - 3.5VREF + DUTGND 216 216
Preliminary Technical Data
Therefore, depending on headroom available, the input to the Force Amplifier may be unipolar positive, or bipolar, either symmetrical or asymmetrical about DUTGND but always within a voltage span of 22.5V. The offset DAC offsets all DAC functions. It also centers the current range, such that zero current always flows at midscale code irrespective of offset DAC setting. Rearranging the transfer function for the DAC output gives the following equation to determine what Offset DAC code is required for a given reference and output voltage range.
216 (VOUT - DUTGND) 4.5 x DACCODE - OFFSETDAC CODE = 3.5VREF 3.5
OFFSET AND GAIN REGISTERS
Where the voltage range must be take into account the +/-4V headroom and footroom requirements for the amplifier and sense resistor and must be within the range -16.25V to 22.5V (22V range + 500mV overrange to allow for correction). Each DAC level contains independent offset and gain control registers that allow the user to digitally trim offset and gain. These registers give the user the ability to calibrate out errors in the complete signal chain, including the DAC, using the internal m and c registers, which hold the correction factors. All registers in the AD5522 are volatile, so need to be loaded on power on during a calibration cycle. The digital input transfer function for each DAC can be represented as x2 = [(m + 1)/ 2n x x1] + (c - 2n - 1) where: x2 = the data-word loaded to the resistor string DAC. x1 = the 16-bit data-word written to the DAC input register. m = code in gain register (default code = 216 - 1.) c = code in offset register (default code = 215) n = DAC resolution (n = 16). The calibration engine is only engaged when data is written to the x1 register. This has the advantage of minimizing the setup time of the device.
OFFSET DAC
The device is capable of forcing a 22.5V (4.5 x VREF) voltage range. Included on chip is one 16 Bit offset DAC (one for all four channels) which allows for adjustment of the voltage range. The useable range is -16.25V to 22.5V. Zero scale gives a fullscale range of 0V to +22.5V, mid scale gives 11.25V, while the most negative useful range is in a range of -16.25V to 6.25V. Full scale loaded to the Offset DAC does not give a useful output voltage range as the output amplifiers are limited by available footroom. The following table shows the effect of the Offset DAC on the other DACs in the device. Table 11. OFFSET DAC Relationship with other DACs with VREF = 5V
Offset DAC Code 0 0 0 32768 32768 32768 42130 42130 42130 60855 60855 60855 65535 DAC Code 0 32768 65535 0 32768 65535 0 32768 65535 0 32768 65535 DAC Output Voltage Range 0.00 V 11.25 V 22.50 V -8.75 V 2.50 V 13.75 V -11.25 V 0.00 V 11.25 V -16.25 -5.00 6.25 Footroom Limitations
CACHED X2 REGISTERS
Each DAC has a number of cached x2 values. These registers store the result of an offset and gain calibration in advance of a mode change. This enables the user to preload registers; allow the calibration engine to calculate the appropriate x2 value and store until ready to change modes. As the data is ready and held in the appropriate register, this enables mode changing be as time efficient as possible. If an update occurs to a DAC register set that is currently part of the operating PMU mode, the DAC output will update immediately (depending on LOAD condition).
Rev. PrL | Page 20 of 45
Preliminary Technical Data
Offset and Gain registers for the FIN DAC
The FIN (force amplifier input) DAC level contains independent offset and gain control registers that allow the user to digitally trim offset and gain. There are six sets of x1, m and c registers, one set (x1, m and c) for the force voltage range, and one set for each of the force current ranges (4 internal current ranges and 1 external current range). Six x2 registers store calculated DAC values ready to load to the DAC register on a mode change.
OFFSET DAC
16 16 16
AD5522
VREF
One buffered analog input supplies all 20 DACs with the necessary reference voltage to generate the required DC levels.
REFERENCE SELECTION
The voltage applied to the VREF pin determines the output voltage range and span applied to the force amplifier, clamp and comparator inputs. This device can be used with a reference input ranging from 2V to 5V, however, for most applications, a reference input of 5V or 2.5V will be sufficient to meet all voltage range requirements. The DAC amplifier gain is 4.5, which gives a DAC output span of 22.5V. The DACs have offset and gain registers which can be used to calibrate out system errors. In addition, the gain register can be used to reduce the DAC output range to the desired force voltage range. The Force DAC will retain 16 bit resolution even with a gain register setting of quarter scale (0x4000). Therefore, from a single 5V reference, it is possible to get a voltage span as high as 22.5V or as low as 5.625V all from one 5V reference. When using the offset and gain registers, the chosen output range should take into account the system offset and gain errors that need to be trimmed out. Therefore, the chosen output range should be larger than the actual, required range. When using low supply voltages, ensure that there is sufficient headroom and footroom for the required force voltage range. Also, note that with a supply differential of less than 18V and a full scale current range requirement, it is necessary to reduce the current measure in amp gain to 5 so the feedback path can swing through the full range. Also, the forced current range will only be the quoted full scale range with an applied reference of 5V or 2.5V (with ISENSE AMP gain = 5). For other voltage/current ranges, the required reference level can be calculated as follows: 1. 2. 3. 4. Identify the nominal range required Identify the maximum offset span and the maximum gain required on the full output signal range. Calculate the new maximum output range including the expected maximum offset and gain errors. Choose the new required VOUTmax and VOUTmin, keeping the VOUT limits centered on the nominal values. Note that AVDD and AVSS must provide sufficient headroom. Calculate the value of VREF as follows: VREF = (VOUTMAX - VOUTMIN)/4.5
VREF X1 REG M REG C REG 16-Bit FIN DAC FIN
16
X2 REG *6
Serial I/F
Figure 12. FIN DAC Registers
Offset and Gain registers for the COMPARATOR DACs
The Comparator DAC levels contain independent offset and gain control registers that allow the user to digitally trim offset and gain. There are six sets of (x1, m and c) registers, one set for the voltage mode, and one set for each of the four internal current ranges and one set for the external current range. In this way, x1 may also be preprogrammed, so switching different modes, allows for efficient switching into the required compare mode. Six x2 registers store cached calculated DAC values ready to load to the DAC register on a mode change.
16 16 16
X1 REG M REG C REG
X2 REG *6
16
16-Bit CPH DAC
CPH
VREF
16 16 16
Serial I/F
X1 REG M REG C REG
16
X2 REG *6
CPL 16-Bit CPL DAC
Figure 13. Comparator Registers
Offset and Gain registers for the Clamp DACs
The clamp DAC levels contain independent offset and gain control registers that allow the user to digitally trim offset and gain. There are just two sets of registers, one for the voltage mode and another register set (x1, m and c) for all five current ranges. Two x2 registers store cached calculated DAC values ready to load to the DAC register on a PMU mode change.
VREF
16 16 16
X1 REG M REG C REG
16
X2 REG
16-Bit CLH DAC
CLH
16 16 16
X1 REG M REG C REG
16
X2 REG
16-Bit CLL DAC
CLL
Serial I/F
Figure 14. Clamp Registers
5.
Rev. PrL | Page 21 of 45
AD5522
Reference Selection Example
Nominal Output Range = 10V (-2V to +8V) Offset Error = 100mV Gain Error = 0.5% REFGND = AGND = 0V 1) Gain Error = 0.5% => Maximum Positive Gain Error = +0.5% => Output Range incl. Gain Error = 10 + 0.005(10)=10.05V Offset Error = 100mV => Maximum Offset Error Span = 2(100mV)=0.2V => Output Range including Gain Error and Offset Error = 10.05V + 0.2V = 10.25V VREF Calculation Actual Output Range = 10.25V, that is -2.125V to +8.125V (centered); VREF = (8.125V + 2.125V)/4.5 = 2.28V
Preliminary Technical Data
12/12.26x 65535 = 64145
Example 1: Gain Error = +0.5%, Offset Error = +100mV
1) Gain Error (0.5%) Calibration: 63937 x 0.995 = 63617 => Load Code "0b1111 1000 1000 0001" to m register 2) Offset Error (100mV) Calibration: LSB Size = 10.25/65535 = 156 V; Offset Coefficient for 100mV Offset = 100/0.156 = 641 LSBs => Load Code "0b0111 1101 0111 1111" to c register
2)
SYSTEM LEVEL CALIBRATION
There are many ways to calibrate the device on power on. The following gives an example of how to calibrate the FIN DAC of the device without a DUT or DUT board connected. Calibration Procedure for Force and Measure circuitry: 1) Calibrate Force Voltage (2 point) Write zero scale to the Force DAC (FIN), connect SYS_FORCE to FOHx and SYS_SENSE to MEASVHx, close the internal Force/Sense Switch (SW 7). Using the System PMU, measure the error between voltage at FOHx, MEASVHx and desired value. Similarly, load Full scale to the Force DAC, and measure the error between FOHx , MEASVH and the desired value. Work out m and c values. Load these values to appropriate m and c registers for Force DAC. Calibrate Measure Voltage (2 point) Connect SYS_FORCE to FOH, SYS_SENSE to MEASVHx Close Internal Force/Sense switch (SW 7). Force voltage on FOH via SYS_FORCE and measure voltage at MEASOUT. The difference is the error between the actual forced voltage and the voltage at MEASOUT. Calibrate Force current (2 point) In Force current mode, write zero and fullscale to the Force DAC. Connect SYS_FORCE to external ammeter and to FOH pin. Measure error on zero and fullscale current and calculate m and c values. Calibrate Measure Current (2 Point) Write zero scale to the Force DAC in Force Current mode. Connect SYS_FORCE to an external ammeter and to the FOH pin. Measure the error between ammeter reading and MEASOUT reading. Repeat with Full scale loaded to the Force DAC. Repeat for all four channels.
3)
If the solution yields an inconvenient reference level, the user can adopt one of the following approaches: 1. 2. Use a resistor divider to divide down a convenient, higher reference level to the required level. Select a convenient reference level above VREF and modify the Gain and Offset registers to digitally downsize the reference. In this way the user can use almost any convenient reference level. Use a combination of these two approaches
2)
3.
In this case, the optimum reference to choose is a 2.5V reference, then use the m and c registers and the OFFSET DAC to achieve the required -2V to +8V range. The ISENSE amplifier gain should be changed to a gain of 5. This ensures a full scale current range of the specified values and also allows optimization of power supplies and minimizes power consumption within the device.
3)
CALIBRATION
The user can perform a system calibration by overwriting the default values in the m and c registers for any individual DAC channels as follows: Calculate the nominal offset and gain coefficients for the new output range (see previous example) Calculate the new m and c values for each channel based on the specified offset and gain errors
4)
5)
Calibration Example
Nominal Offset Coefficient = 32768 Nominal Gain Coefficient = 10/10.25x 65535 = 63937
Similarly, calibrate the comparators and clamp DACs and load the appropriate gain and offset registers. Calibrating these DACs will require some successive approximation to find where the comparator trips or the clamps engage.
Rev. PrL | Page 22 of 45
Preliminary Technical Data CIRCUIT OPERATION
FORCE VOLTAGE, FV
Most PMU measurements are performed while in force voltage and measure current mode, for example, when the device is used as a device power supply, or in continuity or leakage testing. In the force voltage mode, the voltage forced is mapped directly to the DUT. The voltage measure amplifier completes the loop giving negative feedback to the forcing amplifier. See Figure 15. Forced Voltage at DUT = VFIN Where: VFIN = Voltage of the FIN DAC, See VOUT for DAC levels.
EXTFOH CFF
AD5522
INTERNAL RANGE SELECT (5uA, 20uA, 200uA, 2mA)
FIN
DAC
+ Rsense
FOH
OFFSET DAC BIAS TO CENTER IRANGE
EXTMEASIH + +
x5 or x10
10k + EXTMEASIL
MEASOUT
x1/x0.2
-
Rsense up to (64mA)
AGND
MEASVH + +
x1
DUT DUTGND + -
-
Figure 15. Forcing voltage, measuring current
Rev. PrL | Page 23 of 45
AD5522
FORCE CURRENT, FI
In the force current mode, the voltage at FIN is now converted to a current and applied to the DUT. The feedback path is now the current measure amplifier, feeding back the voltage measured across the sense resistor and MEASOUT reflects the voltage measured across the DUT. See Figure 16. For the suggested current ranges, the maximum voltage drop across the sense resistors is 1V, however, to allow for correction of errors, there is some over range available in the current ranges. The maximum full-scale voltage range that can be loaded to the FIN DAC is 11.5V; the forced current may be calculated as follows:
Preliminary Technical Data
FI =
VFIN RSENSE x Gain
Where: FI = Forced Current VFIN = Voltage of the FIN DAC, See VOUT for DAC levels. RSENSE = Selected Sense Resistor Gain of Current Measure Instrumentation amplifier, it may be set (via the serial interface) to 5 or 10. The ISENSE amplifier is biased by the Offset DAC output voltage, in such as way as to center the Measure current output irrespective of the voltage span used. Using the 5k sense resistor and ISENSE gain of 10, the maximum current range possible is 225A. Similarly for the other current ranges, there is an over range of 12.5% to allow for correction.
EXTFOH CFF
INTERNAL RANGE SELECT (5uA, 20uA, 200uA, 2mA)
FIN
DAC
+ Rsense
FOH
EXTMEASIH
OFFSET DAC BIAS TO CENTER IRANGE
+ +
x5 or x10
10k + EXTMEASIL
MEASOUT
x1/x0.2
Rsense up to (64mA)
-
MEASVH
AGND
+ +
x1
DUT DUTGND + -
-
Figure 16. .Forcing current, measuring voltage
Rev. PrL | Page 24 of 45
Preliminary Technical Data SERIAL INTERFACE
The AD5522 contains two high-speed serial interfaces, an SPI compatible, interface operating at clock frequencies up to 50MHz, and an EIA-644-compliant, LVDS interface. To minimize both the power consumption of the device and onchip digital noise, the interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC.
AD5522
the section Power On Default). This sequence takes approx 300s. The falling edge of RESET initiates the reset process; BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled. When BUSY returns high, normal operation resumes and the status of the RESET pin is ignored until it goes low again. The SDO output will be high impedance during a power on reset or a RESET. Power on reset follows the same function as RESET.
SPI INTERFACE
The serial interface operates over a 2.3V to 5.25V DVCC supply range. The serial interface is controlled by four pin, as follows: SYNC Frame synchronization input. SDI Serial data input pin. SCLK Clocks data in and out of the device. SDO Serial data output pin for data readback purposes. There is also an SPI/LVDS select pin, which must be held low for SPI interface and high for LVDS interface.
BUSY AND LOAD FUNCTION
BUSY is an open drain output that indicates the status of the AD5522 interface. When writing to any of the registers BUSY goes low and stays low until the command completes. Writing to a DAC register drives the BUSY signal low for longer than a simple PMU or System Control Register write. For the DACs, the value of the internal cached (x2) data is calculated and stored each time the user writes new data to the corresponding x1 register. During this write and calculation, the BUSY output is driven low. While BUSY is low, the user can continue writing new data to the x1, m, or c registers, but no output updates can take place. X2 values are stored and held until a PMU word is written that calls the appropriate cached x2 register. Only then does a DAC output update. The DAC outputs and PMU modes are updated by taking the LOAD input low. If LOAD goes low while BUSY is active, the LOAD event is stored and the DAC outputs or PMU modes update immediately after BUSY goes high. A user can also hold the LOAD input permanently low. In this case, the change in DAC outputs or PMU modes update immediately after BUSY goes high. The BUSY pin is bidirectional and has a 50 k internal pullup resistor. Where multiple AD5522 devices may be used in one system, the BUSY pins can be tied together. This is useful where it is required that no DAC or PMU in any device is updated until all others are ready. When each device has finished updating the x2 registers, it will release the BUSY pin. If another device has not finished updating its x2 registers, it will hold BUSY low, thus delaying the effect of LOAD going low. As there is only one multiplier shared between four channels, this task must be done sequentially, so the length of the BUSY pulse will vary according to the number of channels being updated.
LVDS INTERFACE
The LVDS interface uses the same input pins as the SPI interface with the same designations. In addition, three other pins are provided for the complementary signals needed for differential operation, thus: SYNC/SYNC Differential frame synchronization signal. SDI/SDI Differential serial data input. SCLK/SCLK Differential clock input. SDO/SDO Serial data output pin for data readback
SERIAL INTERFACE WRITE MODE
The AD5522 allows writing of data via the serial interface to every register directly accessible to the serial interface, which is all registers except the DAC registers. The serial word is 29 bits long. The serial interface works with both a continuous and a burst (gated) serial clock. Serial data applied to SDI is clocked into the AD5522 by clock pulses applied to SCLK. The first falling edge of SYNC starts the write cycle. At least 29 falling clock edges must be applied to SCLK to clock in 29 bits of data, before SYNC is taken high again. The input register addressed is updated on the rising edge of SYNC. In order for another serial transfer to take place, SYNC must be taken low again.
RESET FUNCTION
Bringing the level sensitive RESET line low resets the contents of all internal registers to their power-on reset state (detailed in
Rev. PrL | Page 25 of 45
AD5522
Table 12. BUSY Pulse Width
Action
Preliminary Technical Data
REGISTER UPDATE RATES
BUSY Pulse Width (s max)
0.15
Loading data to PMU, System Control Register or Readback Loading x1 to any 1 PMU DAC Channel Loading x1 to any 2 PMU DAC Channels Loading x1 to any 3 PMU DAC Channels Loading x1 to any 4 PMU DAC Channels
1.25 1.75 2.25 2.75
As mentioned previously the value of the X2 register is calculated each time the user writes new data to the corresponding X1 register. The calculation is performed by a three stage process. The first two stages take 500ns each and the third stage takes 250ns. When the writes to one of the X1 registers is complete the calculation process begins. If the write operation involves the update of a single DAC channel the user is free to write to another register provided that the write operation doesn't finish until the first stage calculation is complete, i.e. 500ns after the completion of the first write operation.
Calibration Engine Time ~600ns WRITE #1 500ns 1st STAGE 500ns 2nd STAGE 1st STAGE 250ns 3rd STAGE 3rd STAGE 3rd STAGE
BUSY Pulse Width = ((Number of channels +1) x 500ns) + 250ns
BUSY also goes low during power-on reset and when a falling edge is detected on the RESET pin.
Calibration Engine Time ~600ns WRITE #1 500ns 1st STAGE 500ns 2nd STAGE 250ns 3rd STAGE
WRITE #2
2nd STAGE 1st STAGE
WRITE #3
3rd STAGE e.g. WRITE TO 3 FIN DAC REGISTERS 3rd STAGE
2nd STAGE
1st STAGE
2nd STAGE
Figure 18. Multiple Single Channel writes engaging calibration engine
1st STAGE
2nd STAGE
WRITE #2
1st STAGE
2nd STAGE
3rd STAGE
Figure 17. Multiple writes to DAC x1 registers
Writing data to the System control register, PMU control register, m or c registers do not involve the digital calibration engine, thus speeding up configuration of the device on power on.
Rev. PrL | Page 26 of 45
Preliminary Technical Data
REGISTER SELECTION
The serial word assignment consists of 29 bits. Bits 28 through to 22 are common to all registers, whether writing to or reading from the device. PMU3 to PMU0 data bits address each PMU channel (or associated DAC register). When PMU3 to PMU0 are all zeros, the System Control Register is addressed. Mode Bits MODE0 and MODE1 address the different sets of DAC registers and the PMU register.
AD5522
PMU Address Bits, PMU3, PMU2, PMU1, PMU0
Bits PMU3 through PMU0 address each of the PMU channels on chip. This allows individual control of each PMU channel or any manner of combined addressing in addition to multi channel programming. PMU bits also allow access to write registers such as the System Control Register and the many DAC registers, in addition to reading from all the registers. Table 13. Mode Bits
B23 MODE1 0 0 1 1
B21 to B0 DATA BITS DATA BITS
Readback Control, RD/WR
The R/W bit set high initiates a readback sequence of PMU, Alarm, Comparator, System Control Register or DAC information as determined by address bits. Table 14. Read and Write Functions of the AD5522
B28 RD/WR B27 PMU3 B26 PMU2 B25 PMU1 0 B24 PMU0 0 B23 MODE1 0 B22 MODE0 0
B22 MODE0 0 1 0 1
WRITE FUNCTION Action System Control Register or PMU Register DAC Gain (m) Register DAC Offset (c) Register DAC Input Data Register, (x1)
SELECTED REGISTER CH3 CH2 CH1
CH0
WRITE FUNCTIONS 0 0 0
Write to System Control Register (Table 16) RESERVED RESERVED NOP (No Operation) RESERVED x x x x CH3 CH3 CH3 x x x CH2 x CH2 CH2 x CH1 CH1 x x CH1 CH1 CHO x CH0 x x x CH0
0 0 0 0 0 0 1 DATA BITS 0 0 0 0 0 1 0 DATA BITS 0 0 0 0 0 1 1 11 1111 1111 1111 1111 1111b 0 0 0 0 0 1 1 DATA BITS other than all 1's WRITE ADDRESSED DAC OR PMU REGISTER 0 0 0 0 1 Select DAC or PMU Registers. DATA BITS See Table 13 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 1 1 1 READ FUNCTIONS 1 0 0 0 0 0 0 All zeros 1 0 0 0 0 0 1 All zeros 1 0 0 0 0 1 0 X 1 0 0 0 0 1 1 All zeros READ ADDRESSED DAC or PMU REGISTER - Can only read one PMU or DAC register at one time. 1 0 0 0 1 PMU/.DAC REGISTER ADDRESS DAC ADDRESS SEE 1 0 0 1 0 SEE Table 13 Table 21 1 0 1 0 0 1 1 0 0 0
Read from System Control Register Read from Comparator Status Registers Reserved Read from Alarm Status Register x x x CH3 x x CH2 x x CH1 x x CH0 x x x
NOP (No Operation)
If a NOP (No Operation) command is loaded, no change is made to DAC or PMU registers. This code is useful when performing a read back of a register within the device (via the SDO pin) where a change of DAC code or PMU function may not be required
Reserved Commands
Any bit combination that is not described in the Register address tables for the PMU, DAC and System Control Registers are Reserved commands. These commands are unassigned commands; they are reserved for factory use. To ensure correct operation of the device, do not used reserved commands.
Rev. PrL | Page 27 of 45
AD5522
WRITE SYSTEM CONTROL REGISTER
Preliminary Technical Data
The System Control Register is accessed when the PMU channel address PMU3-PMU0 and Mode Bits, MODE1 and MODE0 are all zeros. It allows quick setup of different functions within the device. The System Control Register operates on a per device basis. Table 15. System Control Register Bits
B28
RD/WR
B27
PMU3
B26
PMU2
B25
PMU1
B24
PMU0
B23
MODE1
B22
MODE0
B21
CL3
B20
CL2
B19
CL1
B18
CL0
B17
CPOLH3
B16
CPOLH2
B15
CPOLH1
B14
CPOLH0
B13
CPBIASEN
B12
DUTGND/CH
B11
GUARD ALM
B10
CLAMP ALM
B9
INT10K
B8
GUARD EN
B7
GAIN1
B6
GAIN0
B5
TMP ENABLE
B4
TMP1
B3
TMP0
B2
LATCHED
B1/0
0
Table 16. System Control Register Functions
Bit 28 (MSB) 27 26 25 24 Bit name RD/WR PMU3 PMU2 PMU1 PMU0 Description When low, a write function takes place to the selected register, while if the RD/WR bit is set high, this initiates a readback sequence of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits. Bits PMU3 through PMU0 address each of the PMU channels in the device. If all four of this bits are set to zero, the System Control Register is addressed. B27 B26 B25 B24 B23 B22 SELECTED REGISTER PMU3 PMU2 PMU1 PMU0 MODE1 MODE0 CH3 CH2 CH1 CH0 0 0 0 0 0 0 Write to System Control Register x x CHO 0 0 0 1 Select DAC or PMU Registers. x x x CH1 x See below 0 0 1 0 0 0 1 1 1 23 22 MODE1 MODE0 0 1 0 1 1 1 0 0 1 1 1 0 0 0 1
x x CH3 CH3 CH3 x CH2 x CH2 CH2 CH1 x x CH1 CH1 CH0 x x x CH0
Mode Bits, MODE0 and MODE1 allow addressing of the PMU register or the DAC gain (m), offset (c ) or input register (x1). Set to Zero to access the System Control Register. MODE1 MODE0 Action 0 0 System Control Register or PMU Register 0 1 DAC Gain (m) Register 1 0 DAC Offset (c) Register 1 1 DAC Input Data Register, (x1)
SYSTEM CONTROL REGISTER SPECIFIC BITS Clamp Enable. Bits CL3 through CL0 enable and disable the clamp function per channel. A "0" disables, while a "1" enables. The 21 CL3 clamp enable function is also available in the PMU register on a per channel basis. This dual functionality allows flexible enable or 20 CL2 disabling of this function. When reading back information on the status of the clamp enable function, what was most recently 19 CL1 written to the clamp register is available in the readback word from either PMU or System Control Registers. 18 CL0 Comparator Output Enable. By default the comparator outputs are hi-Z on power on. A "1" in each bit position enables the 17 CPOLH3 comparator output for the selected channel. The CPBIASEN (Bit 13) must be enabled to power on the comparator functions. The 16 CPOLH2 comparator enable function is also available in the PMU register on a per channel basis. This dual functionality allows flexible 15 CPOLH1 enable or disabling of this function. When reading back information on the status of the comparator enable function, what was 14 CPOLH0 most recently written to the comparator register is available in the readback word from either PMU or System Control Registers. 13 CPBIASEN Comparator Enable. By default the comparators are powered down on power on. To enable the comparator function for all channels, write a "1" to the CPBIASEN bit. A "0" disabled the comparators and shuts them down. Comparator Output Enables bits (CPOLHx) allow the user to switch on each comparator output individually, enabling bussing of comparator outputs. DUTGND per channel enable. The GUARDIN(0-3)/DUTGND(0-3) pins are shared pin functions and may be configured to enable a DUTGND per PMU channel or GUARD input per PMU channel. Setting this bit to "1" enables DUTGND per channel. In this mode, this pin now functions as a DUTGND pin on a per channel basis. The guard inputs are disconnected from this pin and instead connected directly to the MEASVH line by an internal connection. Default power on condition is GUARDIN(0-3). Clamp and Guard Alarm Function share one open drain CGALM alarm pin. By default, the CGALM pin is disabled. Bits GUARD ALM and CLAMP ALM allow the user to choose if they only wish to have both or either information flagged to the CGALM pin. Set high to enable either alarm function. Internal Sense Short, INT10K. Setting this bit high allows the user to connect in an internal sense short resistor of 10k between the FOH and the MEASVH lines, (closes SW 7), it also closes SW 15, connecting another 10 k resistor between DUTGND and AGND.
Rev. PrL | Page 28 of 45
12
DUTGND/CH
11 10 9
GUARD ALM CLAMP ALM INT10K
Preliminary Technical Data
8 7 6 GUARD EN GAIN1 GAIN0
AD5522
Guard enable. The Guard Amplifier is disabled on power on; write a "1" to enable it. Disabling the guard function if not in use saves power (typically 400A per Channel). MEASOUT Output Range. The MEASOUT range defaults to the voltage force span for voltage and current measurements, this is 11.25V, which includes some over range to allow for offset correction. The MEASOUT range may be reduced by using the GAIN0 and GAIN1 data bits. This allows for use of asymmetrical supplies and also for use of a smaller input range ADC. MEASOUT Function GAIN1 = "1" GAIN1 = "0"VREF = 5V MV MI GAIN0 = "0" GAIN0 = "1" CURRENT MEAS GAIN = 10 CURRENT MEAS GAIN = 5 MEASOUT Gain = 1 VDUT (up to 11.25V) VRSENSE X 10 = up to 11.25V VRSENSE X 5 = up to 5.625 MEASOUT Gain = 1/5
0 to 4.5VREF 5
0 to 4.5V 0 to 2.25V
5 4 3
TMP ENABLE TMP1 TMP0
Thermal Shutdown Function, TMP ENABLE, TMP1, TMP0 To disable the Thermal Shutdown feature, write a "0" to the TMP ENABLE bit (enabled by default). Bits TMP1 and TMP0 allow the user to program the thermal shutdown temperature of operation. TMP ENABLE TMP1 TMP0 Action 0 X X Thermal Shutdown Disabled 1 X X Thermal Shutdown Enabled 1 0 0 Shutdown at Junction Temp of 130C (Power On Default) 1 0 1 Shutdown at Junction Temp of 120C 1 1 0 Shutdown at Junction Temp of 110C 1 1 1 Shutdown at Junction Temp of 100C Configure open drain CGALM as a latched or unlatched output pin. When high, this bit sets the CGALM alarm output as latched outputs allowing it to drive a controller I/O without having to poll the line constantly. Default condition on power on is unlatched. Unused bits. Set to 0.
2 1 0 (LSB)
LATCHED 0 0
Rev. PrL | Page 29 of 45
AD5522
WRITE PMU REGISTER
Preliminary Technical Data
To address PMU functions, set Mode bits MODE1, MODE0 low, this selects the PMU register as outlined in Table 13 and Table 14. The AD5522 has very flexible addressing, in that it allows writing of data to a single PMU channel, any combination of them or all PMU channels. This enables multi pin broadcasting to similar pins on a DUT. Bits 27 to 24 select which PMU or group of PMUs is addressed. Table 17. PMU Register Bits
B28 RD/WR B27 PMU3 B26 PMU2 B25 PMU1 B24 PMU0 B23 MODE1 B22 MODE0 B21 CH EN B20 FORCE1 B19 FORCE0 B18 X B17 C2 B16 C1 B15 C0 B14 MEAS1 B13 MEAS0 B12 FIN B11 SF0 B10 SF0 B9 CL B8 CPOLH B7 COMPARE V/I B6 CLEAR B5 to B0 UNUSED DATA BITS
Table 18. PMU Register Functions
Bit 28 (MSB) 27 26 25 24 Bit name RD/WR PMU3 PMU2 PMU1 PMU0 Description When low, a write function takes place to the selected register, while if the RD/WR bit is set high, this initiates a readback sequence of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits. Bits PMU3 through PMU0 address each of the PMU channels in the device. This allows individual control of each PMU channel or any manner of combined addressing in addition to multi-channel programming. B27 B26 B25 B24 B23 B22 SELECTED REGISTER PMU3 PMU2 PMU1 PMU0 MODE1 MODE0 CH3 CH2 CH1 CH0 0 0 0 0 0 0 Write to System Control Register x x CHO Select DAC or PMU Registers. x 0 0 0 1 See below x x CH1 x 0 0 1 0 0 0 1 1 1 23 22 MODE1 MODE0 0 1 0 1 1 1 0 0 1 1 1 0 0 0 1
x x CH3 CH3 CH3 x CH2 x CH2 CH2 CH1 x x CH1 CH1 CH0 x x x CH0
Mode Bits, MODE0 and MODE1 allow addressing of the PMU register or the DAC gain (m), offset (c ) or input register (x1). Set to zero to access the PMU Register. MODE1 MODE0 Action 0 0 System Control Register or PMU Register 0 1 DAC Gain (m) Register 1 0 DAC Offset (c) Register 1 1 DAC Input Data Register, (x1)
PMU REGISTER SPECIFIC BITS 21 CH EN Channel Enable, Set high to enable the selected channel, similarly, set low to disable a selected channel or group of channels. When disabled, SW 2 is closed, SW 5 open. 20 FORCE1 Bits FORCE1 and FORCE0 address the force function for each of the PMU channels (in association with P3-P0). All combinations of forcing and measuring (using MEAS0 and MEAS1) are available. The Hi-Z (voltage and current) modes allows 19 FORCE0 user to optimize glitch response during mode changes. While in these modes, with PMU Hi-Z, new x1 codes loaded to the FIN DAC register and the Clamp DAC register will be calibrated, stored in x2 register and loaded directly to the DAC outputs. FORCE1 FORCE0 Action 0 0 FV & Current Clamp (if clamp enabled) 0 1 FI & Voltage Clamp (if clamp enabled) 1 0 Hi-Z FOH Voltage (pre load FIN DAC & Clamp DAC) 1 1 Hi-Z FOH Current (pre load FIN DAC & Clamp DAC) 18 17 16 15 RESERVED C2 C1 C0 0 Bits C2 through C0 address allow selection of the required current range. C2 C1 C0 Action 0 0 0 5A current range 0 0 1 20A current range 0 1 0 200A current range 0 1 1 2mA current range 1 0 0 external current range 1 0 1 NOP 1 1 0 NOP 1 1 1 NOP
Rev. PrL | Page 30 of 45
Preliminary Technical Data
14 13 MEAS1 MEAS0
AD5522
Bits MEAS1 and MEAS0 allow selection of the required measure mode, allowing the measout line to be disabled, connected to the temperature sensor or enabled for measurement or current or voltage. MEAS1 MEAS0 Action 0 0 MEASOUT connected to I SENSE 0 1 MEASOUT connected to V SENSE 1 0 MEASOUT connected to Temperature Sensor 1 1 MEASOUT Hi-Z (SW 12 Open) Bit FIN = 0 switches the input of the force amplifier to GND, while FIN = 1 connects it to FIN DAC output. Bits SF0 through SS0 address each of the different combinations of switching the system force and sense lines to the force and sense at the DUT. Selection of which channel the system force and sense lines are connected to as per P3 to P0 addressing. SF0 SS0 Action 0 0 SYS_FORCE and SYS_SENSE Hi-Z 0 1 SYS_FORCE Hi-Z, SYS_SENSE connected to MEASVHx 1 0 SYS_FORCE connected to FOHx, SYS_SENSE Hi-Z 1 1 SYS_FORCE connected to FOHx, SYS_SENSE connected to MEASVHx Per PMU clamp enable bit. A logic high enables the clamp function for the selected PMU. The clamp enable function is also available in the System control register. This dual functionality allows flexible enable or disabling of this function. When reading back information on the status of the clamp enable function on a per channel basis, what was most recently written to the clamp register is available in the readback word from either PMU or System Control Registers. Comparator output enable bit. A logic high enables the comparator output for the selected PMU, the comparator function CPBIASEN must be enabled in the SYSTEM CONTROL REGISTER. The comparator output enable function is also available in the System control register. This dual functionality allows flexible enable or disabling of this function. A logic high selects compare voltage function, while logic low, current function. To clear or reset a latched alarm bit and pin (temperature, guard or clamp), load a "1" to the Clear bit position. This bit applies to latched alarm (clamp and guard) conditions on all four PMU channels. Unused bits. Set to 0.
12 11 10
FIN SFO SSO
9
CL
8
CPOLH
7 6 5 4 3 2 1 0 (LSB)
COMPARE V/I CLEAR 0
Rev. PrL | Page 31 of 45
AD5522
WRITE DAC REGISTER
Preliminary Technical Data
The DAC input, gain and offset registers are addressed through a combination of PMU bits (Bits 27 through 24) and MODE bits (Bits 23 and 22). Bits A5 through A0 address each of the DAC levels on chip. D15 through D0 are the DAC data Bits when writing to these registers. PMU address bits allow addressing to DAC across any combination of PMU channels. Table 19. DAC Register Bits
B28 RD/WR B27 PMU3 B26 PMU2 B25 PMU1 B24 PMU0 B23 MODE1 B22 MODE0 B21 A5 B20 A4 B19 A3 B18 A2 B17 A1 B16 A0 B15 to B0 DATA BITS D15 (MSB to D0 (LSB)
Table 20. DAC Register Functions
Bit 28 (MSB) 27 26 25 24 Bit name RD/WR PMU3 PMU2 PMU1 PMU0 Description When low, a write function takes place to the selected register, while if the RD/WR bit is set high, this initiates a readback sequence of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits. Bits PMU3 through PMU0 address each of the PMU and DAC channels in the device. This allows individual control of each DAC channel or any manner of combined addressing in addition to multi-channel programming. B27 B26 B25 B24 B23 B22 SELECTED REGISTER PMU3 PMU2 PMU1 PMU0 MODE1 MODE0 CH3 CH2 CH1 CH0 0 0 0 0 0 0 Write to System Control Register x x CHO Select DAC or PMU Registers. x 0 0 0 1 See below x x CH1 x 0 0 1 0 0 0 1 1 1 23 22 MODE1 MODE0 0 1 0 1 1 1 0 0 1 1 1 0 0 0 1
x x CH3 CH3 CH3 x CH2 x CH2 CH2 CH1 x x CH1 CH1 CH0 x x x CH0
Mode Bits, MODE0 and MODE1 allow addressing of the DAC gain (m), offset (c ) or input register (x1) MODE1 MODE0 Action 0 0 System Control Register or PMU Register 0 1 DAC Gain (m) Register 1 0 DAC Offset (c) Register 1 1 DAC Input Data Register, (x1) DAC Address Bits. A5 to A3 select which register set is addressed. See Table 21 DAC Address Bits, A2 to A0 select which DAC is addressed. See Table 21 16 DAC Data bits. D15 MSB.
DAC REGISTER SPECIFIC BITS 21,20,19 A5,A4,A3 18,17,16 A2,A1,A0 15 to 0(LSB) D15 (MSB) to D0(LSB)
Rev. PrL | Page 32 of 45
Preliminary Technical Data
DAC Addressing
AD5522
For the FIN and Comparator (CPH & CPL) DACs, there are sets of x1, m and c registers for each current range and for the voltage range, but only two sets for the Clamp function (CLL and CLH). When calibrating the device, m and c registers allow volatile storage of offset and gain coefficients. Calculation of the corresponding DAC x2 register only occurs when x1 data is loaded (no internal calculation occurs on m or c updates). There is one Offset DAC per all four channels in the device, it is addressed through any PMU0-3 address. The Offset DAC only has an input register associated with it; there are no m or c registers for this DAC. When writing to this DAC, set both Mode bits high to address the DAC input register (x1). This address table is also used for readback of a particular DAC address. Table 21. DAC Register Addressing
Register Set A2 to A0 (REGISTER ADDRESS) 000 001 010 011 100 101 110 111
1
5A I range 20A I range 200A I range 2mA I range external I range Voltage range RESERVED RESERVED
Address bits A5 to A3 (DAC ADDRESS Register) 000 001 MODE1 MODE0 RESERVED 0 1 RESERVED 1 0 1 1 OFFSET DAC FIN RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED FIN FIN FIN FIN FIN RESERVED RESERVED
010
011
100
101
110
111
RESERVED RESERVED RESERVED RESERVED CLL I1 CLL V2 RESERVED RESERVED
RESERVED RESERVED RESERVED RESERVED CLH I1 CLH V2 RESERVED RESERVED
CPL CPL CPL CPL CPL CPL RESERVED RESERVED
CPH CPH CPH CPH CPH CPH RESERVED RESERVED
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
CLL I = Clamp Level Low Current register. CLH I = Clamp Level High Current Register. When forcing a voltage, current clamps are engaged, so this register set will be loaded to the Clamp DAC. 2 CLL V = Clamp Level Low Voltage register. CLH V = Clamp Level High Voltage Register. When forcing a current, voltage clamps are engaged, so this register set will be loaded to the Clamp DAC.
Rev. PrL | Page 33 of 45
AD5522
READ REGISTERS
Preliminary Technical Data
Readback of all the registers in the device is possible via the both SPI and LVDS interfaces. In order to readback data from a register, it is first necessary to write a "readback" command to tell the device which register is required to readback. See Table 22 to address the appropriate channel. Table 22. Read Functions of the AD5522
B28 RD/WR B27 PMU3 B26 PMU2 B25 PMU1 B24 PMU0 B23 MODE1 B22 MODE0 B21 to B0 DATA BITS CH3 SELECTED REGISTER CH2 CH1 CH0
READ FUNCTIONS 1 0 0 0 0 0 0 All zeros Read from System Control Register 1 0 0 0 0 0 1 All zeros Read from Comparator Status Registers 1 0 0 0 0 1 0 X Reserved 1 0 0 0 0 1 1 All zeros Read from Alarm Status Register READ ADDRESSED PMU REGISTER - ONLY ONE PMU REGISTER CAN BE READ AT ONE TIME All zeros 1 0 0 0 1 0 0 x x x CH0 1 0 0 1 0 0 0 x x CH1 x 1 0 1 0 0 0 0 x CH2 x x 1 1 0 0 0 0 0 CH3 x x x READ ADDRESSED DAC "m" Register - ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME DAC ADDRESS 1 0 0 0 1 0 1 x x x CH0 SEE Table 21 1 0 0 1 0 0 1 x x CH1 x 1 0 1 0 0 0 1 x CH2 x x 1 1 0 0 0 0 1 CH3 x x x READ ADDRESSED DAC "c" Register - ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME 1 0 0 0 1 1 0 x x x CH0 DAC ADDRESS SEE Table 21 1 0 0 1 0 1 0 x x CH1 x 1 0 1 0 0 1 0 x CH2 x x 1 1 0 0 0 1 0 CH3 x x x READ ADDRESSED DAC "x1" Register - ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME 1 0 0 0 1 1 1 x x x CH0 DAC ADDRESS SEE Table 21 1 0 0 1 0 1 1 x x CH1 x 1 0 1 0 0 1 1 x CH2 x x 1 1 0 0 0 1 1 CH3 x x x
Once the required channel has been addressed, the device will load the 24 bit Readback data into the MSB positions of the 29 Bit serial shift register, the five LSB bits will be filled with zeros. SCLK rising edges clock this readback data out on SDO(framed by the SYNC signal). A minimum of 24 clock rising edges are required to shift the readback data out of the shift register. If writing a 24-bit word to shift data out of the device, user must ensure that the 24 bit write is effectively a NOP (No Operation) command. The last 5 bits in the shift register will always be 00000b, these five bits will become the MSBs of the shift register when the 24 bit write is loaded. To ensure the device receives a NOP command as outlined in Table 14, the recommended flush command is 0xFFFFFF and no change will be made to any register within the device. Readback data may also be shifted out by writing another 29 bit write or read command. If writing a 29-bit command, the readback data will be MSB data available on SDO, followed by 00000b.
Rev. PrL | Page 34 of 45
Preliminary Technical Data
READBACK OF SYSTEM CONTROL REGISTER
The readback function is a 24 bit word, mode, address and System Control Register data bits as shown in the following table. Table 23. Readback System Control Register Data
AD5522
Bit Bit name Description 23 (MSB) MODE1 0 22 MODE0 0 SYSTEM CONTROL REGISTER SPECIFIC READBACK BITS 21 CL3 Readback the status of the individual Clamp Enable bits. A "0" means the clamp is disabled, while a "1" enabled. The clamp enable function is also available in the System Control Register. This dual functionality allows flexible 20 CL2 enable or disabling of this function. When reading back information on the status of the clamp enable function, 19 CL1 what was most recently written to the clamp register from either System Control register or PMU register will be 18 CL0 available in the readback word. 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB) CPOLH3 CPOLH2 CPOLH1 CPOLH0 CPBIASEN DUTGND/CH GUARD ALM CLAMP ALM INT10K GUARD EN GAIN1 GAIN0 TMP ENABLE TMP1 TMP0 LATCHED Unused Readback bits Readback information on the Comparator Output Enable status. A "1" signifies the function is enabled, while a "0" disabled. A logic high indicates that the PMU comparator output is enabled, while if low, it's disabled. The comparator output enable function is also available in the PMU Register. This dual functionality allows flexible enable or disabling of this function. When reading back information on the status of the comparator output enable function, what was most recently written to the comparator register from either System Control register or PMU register will be available in the readback word. This readback bit tells the status of the Comparator Enable function. A "1" in this bit position means the Comparator functions are enabled, while a "0" disabled. DUTGND per channel enable. If this bit is set at "1", DUTGND per channel is enabled, while if "0", individual guard inputs are available per channel. These bits give status on which of these alarm bits trigger the CGALM pin. If this bit is set high, the internal 10k resistor is connected between FOH and MEASVH, and between DUTGND and AGND. If low, they are disconnected. Readback status of the Guard amplifies. If high, Amplifiers are enabled. Status of the selected MEASOUT Output Range. Information is available on the status of the setting for Thermal shutdown function. Refer to System control write register. This bit tells of the status of the open drain outputs. When high, the open drain alarm outputs are latched outputs, while if low, they are unlatched. Will be loaded with zeros.
Rev. PrL | Page 35 of 45
AD5522
READBACK OF PMU REGISTER
The PMU readback function is a 24 bit word, mode, address and PMU data bits.
Preliminary Technical Data
Table 24. Readback PMU Register (Only one PMU register may be read back at any one time).
Bit Bit name 23 (MSB) MODE1 22 MODE0 PMU REGISTER SPECIFIC BITS 21 CH EN 20 FORCE1 19 FORCE0 18 RESERVED 17 C2 16 C1 15 C0 14 MEAS1 13 MEAS0 12 FIN 11 SFO 10 SSO 9 CL Description 0 0 Channel Enable, If high selected channel is enabled, otherwise disabled. These bits tell what force and measure mode the selected channel is in. 0 These three bits tell what forced or measured current range is set for the selected channel.
Bits MEAS1 and MEAS0 tell which measure mode is selected, voltage, current, temperature sensor or HiZ. This bit shows the status of the Force input amplifier. The system force and sense lines may be connected to any of the four PMU channels. Reading back these bits tell if they are switched in or not. A logic high in this readback position tells if the Per PMU clamp is enabled, while if low, the clamp is disabled. The clamp enable function is also available in the System Control Register. This dual functionality allows flexible enable or disabling of this function. When reading back information on the status of the clamp enable function, what was most recently written to the clamp register from either System Control register or PMU register will be available in the readback word. A logic high indicates that the PMU comparator output is enabled, while if low, it's disabled. The comparator output enable function is also available in the System Control Register. This dual functionality allows flexible enable or disabling of this function. When reading back information on the status of the comparator output enable function, what was most recently written to the comparator register from either System Control register or PMU register will be available in the readback word. A logic high selects indicates the selected channel is comparing voltage function, while logic low, current function. TMPALM corresponds to the open drain TMPALM output pin which flags the user of a temperature event exceeding the default or user programmed level. The temperature alarm is a per device alarm, and latched (LTMPALM) and unlatched (TMPALM) bits tell a temperature event occurred and if the alarm still exists (if the junction temperature still exceeds the programmed alarm level). To reset an alarm event, the user must write to the CLEAR bit in the PMU register. Will be loaded with zeros.
8
CPOLH
7 6 5
COMPARE V/I LTMPALM TMPALM
4, 3, 2, 1, 0 (LSB)
Unused Readback bits
READBACK OF COMPARATOR STATUS REGISTER
The Comparator output status Register is a read only register giving access to the output status of each of the comparators on the chip. Table 25 shows the format of the comparator readback word. Table 25. Comparator Status Readback Register
Bit Bit name Description 23 (MSB) MODE1 0 22 MODE0 1 COMPARATOR STATUS REGISTER SPECIFIC BITS 21 CP0L0 Comparator output conditions per channel corresponding to the comparator output pins. 20 CP0H0 19 CP0L1 18 CP0H1 17 CP0L2 16 CP0H2 15 CP0L3 14 CP0H3 13 to 0 (LSB) Unused Readback bits Will be loaded with zeros.
Rev. PrL | Page 36 of 45
Preliminary Technical Data
READBACK OF ALARM STATUS REGISTER
AD5522
The Alarm Status register is a READ only register that gives information on temperature, clamp and guard alarm events. In the event the Guard and Clamp alarm functions are not used, (the alarm function may be switched off in the System Control Register). In this case, the Temperature alarm status is also available in the contents of any of the four PMU readback registers. Table 26. Alarm Status Readback Register
Bit Bit name Description 23 (MSB) MODE1 1 22 MODE0 1 ALARM STATUS READBACK REGISTER SPECIFIC BITS 21 LTMPALM TMPALM corresponds to the open drain TMPALM output pin which flags the user of a temperature event exceeding the default or user programmed level. The temperature alarm is a per device alarm, and latched 20 TMPALM (LTMPALM) and unlatched (TMPALM) bits tell a temperature event occurred and if the alarm still exists (if the junction temperature still exceeds the programmed alarm level). To reset an alarm event, the user must write to the CLEAR bit in the PMU register. 19 LG0 LGx is the per channel latched Guard Alarm bit and Gx is an unlatched alarm bit. These bits give information on which channel flagged an alarm on the open drain alarm CGALM pin and if the alarm 18 G0 condition still exists. 17 LG1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 to 0 (LSB) G1 LG2 G2 LG3 G3 LC0 C0 LC1 C1 LC2 C2 LC3 C3 Unused Readback bits Will be loaded with zeros. LCx is a per channel latched Clamp alarm bit and Cx is the unlatched alarm bit. These bits give information on which channel flagged an alarm on the open drain alarm CGALM pin and if the alarm condition still exists.
READBACK OF DAC REGISTER
The DAC readback function is a 24 bit word, mode, address and DAC data bits. Table 27. DAC Register Readback
Bit Bit name 23 (MSB) MODE1 22 MODE0 DAC READBACK REGISTER SPECIFIC BITS 21 to 16 A5, A4, A3, A2, A1 15 to 0 (LSB) D15 to D0 Description 0 0 Address Bits indicating the DAC register that is read. Contents of the addressed DAC register (x1, m or c).
Rev. PrL | Page 37 of 45
AD5522
POWER ON DEFAULT
Preliminary Technical Data
The power on default for all DAC channels is that the contents of each m register is set to full-scale (0xFFFF) and c register to midscale(0x8000). The contents of the DAC registers are : Offset DAC: 0xA492, FIN DACs: 0x8000, CLL DACs: 0x0000, CLH DACs: 0xFFFF, CPL DACs: 0x0000, CPH DACs: 0xFFFF The power on defaults of the PMU register and the System Control Register are shown below. Table 28. Power on Default for System Control Register and PMU Register
Bit 21 (MSB) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB) SYSTEM CONTROL REGISTER POWER ON DEFAULT Bit name Description CL3 0 CL2 0 CL1 0 CL0 0 CPOLH3 0 CPOLH2 0 CPOLH1 0 CPOLH0 0 CPBIASEN 0 DUTGND/CH 0 GUARD ALM 0 CLAMP ALM 0 INT10K 0 GUARD EN 0 GAIN1 0 GAIN0 0 TMP ENABLE TMP1 TMP0 LATCHED Unused Data Bits 1 0 0 0 0 0 PMU REGISTER POWER ON DEFAULT Bit name Description CH EN 0 FORCE1 0 FORCE0 0 RESERVED 0 C2 0 C1 1 C0 1 MEAS1 1 MEAS0 1 FIN 0 SFO 0 SSO 0 CL 0 CPOLH 0 COMPARE V/I 0 LTMPALM 1 TMPALM Unused Data Bits 1 0 0 0 0 0
Rev. PrL | Page 38 of 45
Preliminary Technical Data
SETTING UP THE DEVICE ON POWER ON
On power on, default conditions are recalled from the power on reset register ensuring each PMU and DAC channel is powered up to a known condition. To operate the device, the user must: 1) 2) Configure the device by writing to the System Control register to set up different functions as required. Calibrate out errors and load required calibration values to (Gain) m and (Offset) c registers, and load codes to each DAC input register (x1). Once x1 values are loaded to the individual DACs, the calibration engine calculates the appropriate x2 value and stores it ready for the PMU address to call it. Load the required PMU channel with the required force mode, current range etc. Loading the PMU channel configures the switches around the Force Amplifier, Measure function, clamps and comparators and also acts as a load signal for the DACs, loading the DAC register with the appropriate stored x2 value. As the voltage and current ranges have individual DAC registers associated with them, each PMU register mode of operation calls a particular x2 register. Hence, only updates (changes to x1 register) to DACs associated with the selected mode of operation are reflected to the output of the PMU. If there is a change to the x1 value associated with a different PMU mode of operation, then this x1 value and it's m and c coefficients are used to calculate a corresponding x2 value which is stored in the correct x2 register, but it does not get loaded to the DAC.
AD5522
CHANGING MODES
There are different ways of handling a mode change: 1) Load any DAC x1 values that are required to change. Remember that x1 registers are available per voltage and current range (for Force Amplifier and Comparator DACs), so you can preload these and may not need to make changes. The calibration engine will calculate the x2 values and store them. Now change into the new PMU mode. This will load the new switch conditions in the PMU circuitry and load the DAC register with the stored x2 data.
2)
or 1) 2) Use the Hi-Z V or Hi-Z I mode in the PMU register, this makes the amplifier high impedance. Now load any DAC x1 values that need to be loaded. Remember that x1 registers are available per voltage and current range, so you can preload these and may not need to make changes. When the Hi-Z (V or I) modes are used, the relevant DAC outputs are automatically updated (FIN, CLL, CLH DACs). For example, when selecting Hi-Z V (Voltage), the FIN Voltage x2 result is loaded, offset and gain corrected, cached and loaded to the FIN DAC. When forcing a voltage, current clamps are engaged, so the CLL I (Current) register can be loaded, gain and offset corrected and loaded to the DAC register. Similarly, for the CLH I register. Now change into the new PMU mode (FI/FV). This will load the new switch conditions in the PMU circuitry. As the DAC outputs are already loaded, transients when changing current or voltage mode will be minimized.
3)
4)
3)
4)
Rev. PrL | Page 39 of 45
AD5522
REQUIRED EXTERNAL COMPONENTS
The minimum required external components are shown in the block diagram below. Decoupling will be very dependent on the type of supplies used, other decoupling on the board and the noise in the system. It is possible more or less decoupling may be required as a result.
AVSS
10F
Preliminary Technical Data
AVDD DVCC
10F 10F
REF
0.1F
0.1F
0.1F
0.1F
AVSS
AVDD
DVCC
VREF
CCOMP(0-3) EXTFOH3 CFF3 FOH3 MEASVH3 EXTMEASIH3 up to 64mA
EXTFOH0 CFF0 FOH0 MEASVH0 EXTMEASIH0 up to 64mA EXTMEASIL0
EXTMEASIL3
DUT
DUT
EXTFOH1 CFF1 FOH1 MEASVH1 EXTMEASIH1 up to 64mA EXTMEASIL1 DUTGND
EXTFOH2 CFF2 FOH2 MEASVH2 EXTMEASIH2 up to 64mA EXTMEASIL2
DUT
DUT
Figure 19. External components required for use with this PMU device.
Rev. PrL | Page 40 of 45
Preliminary Technical Data
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5522 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5522 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (AVSS, AVDD, VCC), it is recommended to tie these pins together and to decouple each supply once. The AD5522 should have ample supply decoupling of 10 F in parallel with 0.1 F on each supply located as close to the package as possible, ideally right up against the device. The 10F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Digital lines running under the device should be avoided, because these couple noise onto the device. The analog ground plane should be allowed to run under the AD5522 to avoid noise coupling (only with the package with paddle up).. The power supply lines of the AD5522 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. It is essential to minimize noise on all VREF lines. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. As is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. Also note that the exposed paddle of the AD5522 is connected to the negative supply AVSS.
AD5522
Rev. PrL | Page 41 of 45
AD5522
TYPICAL APPLICATION FOR THE AD5522
Figure 20 shows the AD5522 as used in an ATE system. This device can used as a per pin parametric unit in order to speed up the rate at which testing can be done. The central PMU shown in the block diagram is usually a highly accurate PMU, and is shared among a number of pins in the tester. In general, many discrete levels are required in an ATE system for the pin drivers, comparators, clamps, and active loads. DAC devices, such as the AD5379, offer a highly integrated solution for a number of these levels. The AD5379 is a dense 40-channel DAC designed with high channel requirements, such as ATE .
Preliminary Technical Data
Driven Shield DAC Central PMU ADC DAC DAC DAC Formatter De-Skew DAC DAC DAC Compare Memory Formatter De-Skew DAC DAC DAC DAC IOH IOL VCOM VTH Comp VTL DAC
Device Power supply
Guard Amp
AD5522
VCH ADC
DAC
Vterm VH
PPMU
Timing Data Memory
DUT Relays
50 Coax
Timing Generator DLL,Logic
Driver VL VCL Guard Amp GND Sense
ADC Active Load
Figure 20. Typical Applications Circuit using the AD5522 as a per pin parametric unit.
Rev. PrL | Page 42 of 45
Preliminary Technical Data OUTLINE DIMENSIONS
14.20 14.00 SQ 13.80 0.75 0.60 0.45 1.20 MAX
80 1 PIN 1
AD5522
12.20 12.00 SQ 11.80
61 60 60 61 80 1
TOP VIEW
(PINS DOWN)
EXPOSED PAD
9.50 BSC SQ
1.05 1.00 0.95
0 MIN
BOTTOM VIEW
(PINS UP) 20 21 40 41 41 40 20 21
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
Figure 21. 80 lead TQFP/EP with exposed pad on bottom
14.20 14.00 SQ 13.80 0.75 0.60 0.45 1.20 MAX
80 1 PIN 1
12.20 12.00 SQ 11.80
61 60 60 61 80 1
EXPOSED PAD
9.50 BSC
BOTTOM VIEW
(PINS UP)
1.05 1.00 0.95
0 MIN
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
TOP VIEW
(PINS DOWN) 20 21 40 41 41 40 20 21
VIEW A
6.50 BSC
0.50 BSC LEAD PITCH
0.27 0.22 0.17
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HU
Figure 22. 80 lead TQFP/EP with exposed pad on top
Rev. PrL | Page 43 of 45
AD5522
ORDERING GUIDE
Model AD5522JSVDZ2 Function Quad PMU with 4 internal current ranges, full comparator function, 1 external current range, SPI and LVDS serial interfaces. Quad PMU with 4 internal current ranges, full comparator function, 1 external current range, SPI and LVDS serial interfaces. Quad PMU, 4 internal current ranges, window comparator function, SPI interface.
Preliminary Technical Data
Package Description1 80 Lead TQFP with exposed pad on bottom
Package Options SV-80
AD5522JSVUZError!
Bookmark not defined.
80 Lead TQFP with exposed pad on top
SV-80
AD5523JCPZError!
Bookmark not defined.,3
1 2 3
64 Lead LFCSP with exposed pad on bottom 9mm x 9mm
CP-64
Exposed pad is tied to AVSS.
Lead Free. Reduced functionality. Contact factory for AD5523 datasheet and more details..
Rev. PrL | Page 44 of 45
Preliminary Technical Data NOTES
AD5522
(c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. PR06197-0-9/06(PrL)
Rev. PrL | Page 45 of 45

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